Reducing leakage current in a memory device

A memory device, comprising:

• a column of memory cells, each memory cell being arranged to store a data value;
• a pair of bit lines coupled to said column of memory cells;
• bit line precharge circuitry for precharging said pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in said column is selected in an evaluate phase following said precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell;
• power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging said pair of bit lines;
• selector circuitry arranged when the memory device is to enter said power down mode to ensure that none of said memory cells in said column are selected;
• a plurality of said columns of memory cells;
• a corresponding plurality of said pairs of bit lines;
• a plurality of word lines, each word line being coupled to one of said memory cells in each column;
• said selector circuitry being arranged to drive one of said word lines in said evaluate phase to cause the memory cells coupled to that word line to be selected,
• wherein said selector circuitry comprises;
• a dynamic node coupled to a corresponding word line;
• dynamic node precharge circuitry arranged during said precharge phase to precharge the dynamic node to a first voltage level;
• evaluation circuitry arranged to receive a number of input signals and during said evaluate phase to selectively drive the dynamic node to a second voltage level dependent on the input signals;
• and
• power down drive circuitry arranged when the selector circuitry is to enter a power down mode to drive the dynamic node to the second voltage level.

A method of operating a memory device to reduce leakage current in a power down mode of operation, the memory device comprising a column of memory cells, each memory cell being arranged to store a data value, a pair of bit lines coupled to said column of memory cells, and bit line precharge circuitry for precharging said pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in said column is selected in an evaluate phase following said precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell, the method comprising the steps of:

• (a) preventing the bit line precharge circuitry from precharging said pair of bit lines when the memory device is to enter a power down mode;
• and
• (b) ensuring that none of said memory cells in said column are selected when the memory device is to enter said power down mode,
• wherein said memory device further comprises a plurality of said columns of memory cells, a corresponding plurality of said pairs of bit lines, a plurality of word lines, each word line being coupled to one of said memory cells in each column, and selector circuitry arranged to drive one of said word lines in said evaluate phase to cause the memory cells coupled to that word line to be selected,
• wherein said selector circuitry comprises a dynamic node coupled to a corresponding word line, dynamic node precharge circuitry arranged during said precharge phase to precharge the dynamic node to a first voltage level, and evaluation circuitry arranged to receive a number of input signals and during said evaluate phase to selectively drive the dynamic node to a second voltage level dependent on the input signals, the method further comprising the step of:
• driving the dynamic node to the second voltage level when the selector circuitry is to enter a power down mode.