Memory tile for use in a tiled memory
AssigneesMadrone Solutions, Inc., Motorola, Inc.
InventorsMichael L. Longwell, William Daune Atwell, Jeffrey Van Myers
Life of this patent
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Abstract
A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c′, 32c″).
Claims244
A memory tile for use in a tiled memory adapted to be connected to first and second power supply potentials external to said tiled memory via respective first and second connectors, the memory tile comprising:
- a plurality of memory cells coupled to receive power via said first and second connectors;
- and
- a charge source coupled to receive power via said first and second connectors, the charge source sourcing charge at a third potential different from said first and second power supply potentials for use within said memory tile.
An integrated circuit having a memory tile for use in a tiled memory adapted to be connected to first and second power supply potentials external to said tiled memory via respective first and second connectors, the memory tile comprising:
- a plurality of memory cells coupled to receive power via said first and second connectors;
- and
- a charge source coupled to receive power via said first and second connectors, the charge source sourcing charge at a third potential different from said first and second power supply potentials for use within said memory tile.
Dependencies are inferred from the claim text.