Single bitline direct sensing architecture for high speed memory device

A sense amplifier circuit for a memory device, wherein the read function is performed solely by a set of four transistors and a current source comprising:

• a current source coupled to a read data line to supply charge to the read data line;
• a first transistor having a control gate and a current path, the control gate coupled to a first read enable signal of the memory array, the current path coupled between the read data line and a current path of a second transistor;
• the second transistor having a control gate and a current path, the control gate coupled to a first bitline of the memory array, the current path coupled between the current path of the first transistor and a ground potential;
• a third transistor having a control gate and a current path, the control gate coupled to a second read enable signal of the memory array, the current path coupled between the read data line and a current path of a fourth transistor;
• the fourth transistor having a control gate and a current path, the control gate coupled to a second bitline of the memory array, the current path coupled between the current path of the third transistor and a ground potential;
• wherein the first and second read enable signals which are coupled to the control gates of the first and third transistors, respectively, are utilized to provide multiplexing between the first and second bitlines to the read data line during a read operation.

A dynamic random access memory comprising:

• an array of storage cells arranged in rows and columns, each column including a bitline pair coupled to a plurality of the memory cells;
• a control circuit which generates two read control signals;
• an output buffer circuit which outputs data signals;
• a read data line coupled to the output buffer circuit;
• and
• a direct sense amplifier circuit having control terminals coupled to receive the read control signals, the direct sense amplifier circuit applying data from one of the two bitlines of the bitline pair to the read data line in response to the read control signals.

A method of writing and reading data in a memory device including the steps of:

• applying datum to a data line;
• applying a pair of write control signals to the control gate of a first transistor with a current path connected between the data line and a first bitline, and also to the control gate of a second transistor with a current path connected between the data line and a second bitline, the write control signals are applied to turn on the first transistor and turn off the second transistor in order to allow the datum on the data line to be applied to the first bitline, or vice versa;
• storing the datum in a memory cell connected to the first bitline;
• applying a pair of read control signals to the control gate of a third transistor with a current path connected in series with a current path of a fourth transistor and a ground potential, and also to the control gate of a fifth transistor with a current path connected in series with a current path of a sixth transistor and a ground potential, the read control signals applied to turn on the third transistor and turn off the fifth transistor to allow the current path of the fourth transistor, and the voltage on the data line, to be controlled by the signal on the first bitline which is coupled to the control gate of the fourth transistor, or vice versa.

A semiconductor memory device comprising:

• a memory array comprising at least one bitline pair, each comprising a
• true bitline and a complement bitline;
• a first means to selectively couple either the true bitline or the complement bitline of said at least one bitline pair to a first data line, while the other uncoupled bitline is precharged in a read mode;
• a second means to selectively couple either the true bitline or the complement bitline of said at least one bitline pair to a second data line, while the other uncoupled bitline is precharged in a write mode.

A semiconductor memory device comprising:

• first memory array and a second memory array, wherein each of said memory arrays comprises at least one bitline pair, each comprising a true bitline and a complement bitline controlled by first and second means;
• the first means in the first memory array to selectively couple either the true bitline or the complement bitline of said at least one bitline pair to a first data line, while the other uncoupled bitline is precharged in a read mode,
• the second means in the second memory array selectively couples either the true bitline or the complement bitline of said at least one bitline pair to a second data line, while the other uncoupled bitline is precharged in a write mode;
• thus enabling a read mode and a write mode for the first and second memory arrays simultaneously.

Within an integrated circuit, a method of sensing first and second stored bit signals from a first bitline and from a second bitline for output onto a single-ended output data line, comprising:

• precharging first and second bitlines to a predetermined level;
• transferring a stored bit signal onto said first bitline;
• first applying said first stored bit signal from said first bitline to a control terminal of a first control device coupled to a single-ended output data line to control an output signal level on said single-ended output data line according to a level of said stored bit signal, said first control device being placed in a current path between said single-ended output data line and a fixed potential;
• timing said step of first applying with a first read timing signal applied only to a first read timing device placed in a current path between said single-ended data line and a fixed potential;
• precharging said first and second bitlines to a predetermined level;
• transferring a second stored bit signal onto said second bitline;
• second applying said second stored bit signal from said second bitline to a control terminal of a second control device coupled to the single-ended output data line to control an output signal level on said single-ended output data line according to a level of said second stored bit signal, said second control device being placed in a current path between said single-ended output data line and the fixed potential;
• timing said step of second applying with a second read timing signal applied only to a first read timing device placed in a current path between said single-ended data line and the fixed potential.