Sense amplifier for dynamic random access memory (“DRAM”) devices having enhanced read and write speed

A sense amplifier circuit for an integrated circuit memory comprising:

• first and second complementary bit lines;
• first and second complementary latch nodes;
• and
• first and second MOS transistors respectively coupling said first bit line to said first latch node and said second bit line to said second latch node, said first and second MOS transistors having a control terminal thereof coupled to a constant voltage source greater than a supply voltage level supplied to said sense amplifier circuit.

A sense amplifier circuit for an integrated circuit memory comprising:

• first and second complementary bit lines;
• first and second complementary latch nodes;
• and
• first and second depletion transistors including control terminals thereof coupled to a constant supply voltage greater than a supply voltage level supplied to said sense amplifier circuit level respectively coupling said first bit line to said first latch node and said second bit line to said second latch node.

A sense amplifier circuit for an integrated circuit memory comprising:

• first and second complementary bit lines;
• first and second complementary latch nodes;
• and
• first and second CMOS pass gates respectively coupling said first bit line to said first latch node and said second bit line to said second latch node, each of said pass gates comprising a parallel coupled P-channel and N-channel transistor, wherein each of said P-channel and N-channel transistors include a control terminal thereof, said control terminals of said P-channel transistors being coupled to a constant reference voltage level and said control terminals of said N-channel transistors being coupled to a constant supply voltage level greater than a supply voltage level supplied to said sense amplifier circuit.

A sense amplifier circuit for an integrated circuit memory comprising:

• a single pair of bit lines including:
• first and second complementary bit lines;
• first and second complementary latch nodes;
• first and second unclocked N-channel MOS transistors each having a control terminal coupled to a constant voltage source having a voltage level greater than a supply voltage level supplied to said sense amplifier circuit respectively coupling said first bit line to said first latch node and said second bit line to said second latch node;
• and
• a latch circuit coupled between said first and second latch nodes.

A sense amplifier circuit for an integrated circuit memory comprising:

• a single pair of bit lines including:
• first and second complementary bit lines;
• first and second complementary latch nodes;
• and
• first and second MOS transistors respectively coupling said first bit line to said first latch node and said second bit line to said second latch node, said first and second MOS transistors having a control terminal thereof coupled to a constant voltage source having a voltage level greater than a supply voltage level supplied to said sense amplifier circuit.