Data line precharging circuit of a semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyung-Gon Kim, Seok-Cheon Kwon
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device has at least one data line, registers for storing data bits, and switch elements corresponding to the registers for transferring the data bits to the data line in response to corresponding selection signals. It also has a precharge circuit connected to the data line, for precharging the data line to a power supply voltage in response to a precharge control signal. The selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and the precharge control signal is activated during the interval of the selection signals, by synchronously responding to the clock signal.
Claims7
A semiconductor memory device comprising:
- at least one data line;
- a plurality of registers for storing data bits;
- a plurality of switch elements corresponding to the registers for transferring the data bits of the corresponding registers to the data line in response to corresponding selection signals;
- and
- a precharge circuit connected to the data line for precharging the data line to a power supply voltage in response to a precharge control signal, the precharge circuit including a depletion MOS transistor, wherein
- the selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and
- the precharge control signal is activated during the interval of the selection signals by synchronously responding to the clock signal.
A semiconductor memory device comprising:
- at least one data line;
- a plurality of registers for storing data bits;
- a plurality of switch elements corresponding to the registers for transferring the data bits of the corresponding registers to the data line in response to corresponding selection signals;
- and
- a precharge circuit connected to the data line for precharging the data line to a power supply voltage in response to a precharge control signal, said precharge circuit including a depletion MOS transistor having a current path connected between the power supply voltage and the data line, and a gate coupled with the data line, wherein
- the selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and
- the precharge control signal is activated during the interval of the selection signals by synchronously responding to the clock signal.
A semiconductor memory device comprising:
- at least one data line;
- a plurality of registers for storing data bits;
- a plurality of switch elements corresponding to the registers for transferring the data bits of the corresponding registers to the data line in response to corresponding selection signals;
- and
- a precharge circuit connected to the data line for precharging the data line to a power supply voltage in response to a precharge control signal, said precharge circuit including a P-channel metal oxide semiconductor (PMOS) transistor having a current path connected between the power supply voltage and the data line, a gate coupled with the precharge control signal, and a depletion MOS transistor having a current path connected between the power supply voltage and the data line, and a gate coupled with the data line, wherein
- the selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and
- the precharge control signal is activated during the interval of the selection signals by synchronously responding to the clock signal.
Dependencies are inferred from the claim text.