Method and apparatus for identifying SRAM cells having weak pull-up PFETs

A method for determining the memory cell stability of individual memory cells included within a memory array, the method comprising:

• presetting each memory cell to a first logic state;
• applying a gradually increasing, controlled leakage current to a node within each memory cell;
• and
• monitoring the voltage of each of said nodes within each corresponding memory cell;
• and
• for each memory cell within the memory array, determining the level of leakage current which causes the memory cell to be changed from said first logic state to a second logic state.

A test circuit for a memory device, the memory device having at least one memory cell, a bit line and a complementary bit line, the test circuit comprising:

• a first pull-down transistor;
• a second pull-down transistor;
• a first pull-up transistor;
• a second pull-up transistor;
• a first pass gate, said first pass gate selectively coupling said first pull-down transistor to the bit line;
• and
• a second pass gate, said second pass gate selectively coupling said second pull-down transistor to the complementary bit line;
• said first and second pass gates further being capable of adjustably controlling a preselected magnitude of leakage current applied to the memory cell during a test thereof.

A computer memory device, comprising:

• an array of individual memory cells, arranged in rows and columns;
• and
• a plurality of test circuits, coupled to each of said columns, each of said plurality of test circuits further comprising:
• a first pull-down transistor;
• a second pull-down transistor;
• a first pull-up transistor;
• a second pull-up transistor;
• a first pass gate, said first pass gate selectively coupling said first pull-down transistor to a bit line associated with each column;
• and
• a second pass gate, said second pass gate selectively coupling said second pull-down transistor to a complementary bit line associated with each column;
• said first and second pass gates further being capable of controlling a preselected magnitude of leakage current applied to the memory cell during a test thereof.