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US 6,552,939 B1Granted
Semiconductor memory device having disturb test circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakeo Miki, Kiyohiro Furutani
Life of this patent
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Abstract
In a semiconductor memory device having normal circuit blocks (NBL) and a redundant circuit block (RBL) for replacement, a test mode setting unit (14, 19) sets a spare non-selection mode (TMSPROFF) and enables to restore an original address of a normal circuit (DE) in a state before executing a replacement to thereby implement a disturb test even after the replacement.
Claims4
A semiconductor memory device comprising:
- normal circuit blocks having a plurality of memory cells;
- a redundant circuit block having a plurality of redundant memory cells for replacement during a replacement operation of defective normal memory cells in the normal circuit blocks;
- memory operation circuitry configured to activate the normal circuit blocks and the redundant circuit block for respective cell addresses in a normal mode;
- test mode executing circuitry configured to cause the memory operation circuitry to activate in a test mode the normal circuit blocks and the defective normal memory cells in a state prior to executing the replacement operation;
- and
- logical circuitry configured to activate in the test mode, the normal circuit blocks, the defective normal memory cells, and the redundant circuit block.
3 more elements
Dependencies are inferred from the claim text.