Column redundancy system and method for embedded DRAM devices with multibanking capability

An integrated circuit device, comprising:

• a memory array configured into a series of individual memory blocks, each of said memory blocks having a page structure organized into columns and data lines;
• and
• a column redundancy system serving each of said memory blocks in said memory array, said column redundancy system further comprising:
• a steering logic network for coupling a memory input/output (I/O) device to each of said memory blocks in said memory array;
• and
• a storage register in communication with said steering logic network, said storage register for storing decoded location information for defective data lines in said memory blocks;
• wherein, during a memory operation, said decoded location information stored in said storage register is transmitted to said steering logic network, said storage register further having said decoded location information loaded therein prior to said memory operation, and said steering logic network thereby preventing any of said defective data lines from being coupled to said I/O device.

A method for bypassing a defective memory element in a memory array, the method comprising:

• configuring a storage register in communication with a steering logic network, said steering logic network for coupling a memory input/output (I/O) device to the memory array;
• loading said storage register with decoded defective element location information;
• and
• during a memory operation, transmitting said decoded defective element information from said storage register to said steering logic network, said storage register having said decoded defective location information loaded therein prior to said memory operation;
• wherein said steering logic network is caused to prevent the defective memory element from being coupled to said I/O device.