Semiconductor storage apparatus

A semiconductor integrated circuit device comprising:

• a memory cell array;
• a row decoder which selects a row of said memory cell array;
• 2n sense amplifiers which sense 2n data corresponding to n-bits addresses;
• a column gate in which two or more stages are connected in series, and which selects a column of said memory cell array and electrically connects said selected column to said sense amplifier;
• a column gate driving circuit which selects and drives said column gate;
• 2n data latches which latch said 2n data sensed by said 2n sense amplifiers;
• and
• a multiplexer which sequentially selects said data corresponding to a predetermined address from said 2n data latched by said 2n data latches.

A semiconductor integrated circuit device comprising:

• a first memory cell array in which nonvolatile memory cells are disposed;
• a first row decoder which selects a row of said first memory cell array;
• a reading sense amplifier which senses a plurality of data corresponding to a plurality of addresses from said first memory cell array;
• a first reading column gate in which two or more stages are connected in series, and which selects a column of said first memory cell array and electrically connects said selected column to said reading sense amplifier;
• a first reading column gate driving circuit which selects and drives said first reading column gate;
• a data latch which latches said plurality of data sensed by said reading sense amplifier;
• a multiplexer which sequentially selects said data corresponding to a predetermined address from said plurality of data latched by said data latch;
• a verifying sense amplifier which senses said data corresponding to at least one address from said first memory cell array;
• a first verifying column gate which is connected in parallel to said first reading column gate, and which selects said column of said first memory cell array and electrically connects said selected column to said verifying sense amplifier;
• and
• a first verifying column gate driving circuit which selects and drives said first verifying column gate.

A semiconductor integrated circuit device comprising:

• a plurality of memory cells;
• a selection circuit which selects a plurality of memory cells corresponding to a plurality of addresses from said plurality of memory cells;
• a sense amplifier which senses a plurality of data from said selected plurality of memory cells;
• a data latch which latches said plurality of data sensed by said sense amplifier;
• a multiplexer which selects said data corresponding a predetermined address from said plurality of data latched by said data latch;
• and
• an output circuit which sequential outputs said selected data in synchronization with an external clock,
• wherein a pipeline reading function is disposed to select and sense said memory cell corresponding to the next plurality of addresses from said plurality of memory cells, while said selected data is sequential outputted in synchronization with said external clock,
• a timing for latching said plurality of data, a timing for selecting said memory cell corresponding to said next plurality of addresses, and a timing for selecting the data corresponding to said predetermined address are controlled by a signal generated in synchronization with said external clock, and
• a timing associated with data reading other than said timings is controlled by a signal generated irrespective of said external clock.

A semiconductor integrated circuit device comprising:

• a plurality of memory cells;
• an address control circuit which controls an address;
• a selection circuit which selects a plurality of memory cells corresponding to a plurality of addresses from said plurality of memory cells;
• a sense amplifier which senses a plurality of data from said selected plurality of memory cells;
• a first data latch which latches said plurality of data sensed by said sense amplifier;
• a first transmission gate which transmits said plurality of data sensed by said sense amplifier to said first data latch;
• a multiplexer which selects some data from said plurality of data latched by said first data latch;
• a second data latch which latches said data selected by said multiplexer;
• a second transmission gate which transmits said data selected by said multiplexer to said second data latch;
• and
• an output circuit which sequential outputs said data latched by said second transmission gate in synchronization with an external clock,
• wherein a pipeline reading function is disposed to select and sense the memory cell corresponding to the next plurality of addresses from said plurality of memory cells, while said selected data is sequential outputted in synchronization with said external clock,
• said address control circuit transmits said plurality of data sensed by said sense amplifier to said first data latch, and changes an internal address, and
• said multiplexer selects the next data, while said data selected by said multiplexer is transmitted to said second data latch.