Dual bank flash memory device and method

A method of operating a nonvolatile memory device having a plurality of core banks of nonvolatile memory cells, comprising:

• initially maintaining memory bank configuration information corresponding to grouping of the core banks of nonvolatile memory cells;
• grouping the core banks of nonvolatile memory cells based upon the memory bank configuration information so as to form at least two independently accessible groups of one or more core banks that are each capable of having memory read operations and memory modify operations performed on nonvolatile memory cells therein;
• and
• controlling the groups so that a memory read operation is selectively performed on one of the groups of nonvolatile memory cells while a memory modify operation is being performed on another of the groups.

A nonvolatile memory device, comprising:

• more than two core banks of nonvolatile memory cells, memory cells in each core bank being arranged in addressable rows and columns of nonvolatile memory cells, and each column of memory cells in a core bank being coupled to a distinct column line in the core bank, the more than two core banks being user configurable into two groups of core banks;
• a plurality of address decode circuits, each address decode circuit being associated with a distinct core bank of nonvolatile memory cells and adapted to connect addressed memory cells to a plurality of column lines in the core bank of nonvolatile memory cells associated with the address decode circuit;
• a plurality of sense amplifiers coupled to the column lines in the core banks;
• data output circuitry connected to sense output signals generated by a first set of sense amplifiers;
• control circuitry for receiving input control signals and selectively controlling execution of memory read and memory modify operations on nonvolatile memory cells in any of the core banks, a memory read operation being capable of being performed in any group of core banks in which a memory modify operation is not being performed.

A nonvolatile memory device, comprising:

• more than two core banks of nonvolatile memory cells, memory cells in each core bank being arranged in addressable rows and columns of nonvolatile memory cells, and each column of memory cells in a core bank being coupled to a distinct column line in the core bank;
• a plurality of address decode circuits, each address decode circuit being associated with a distinct core bank of nonvolatile memory cells and adapted to connect addressed memory cells to a plurality of column lines in the core bank of nonvolatile memory cells associated with the address decode circuit;
• a plurality of sense amplifiers coupled to the column lines in the core banks, the sense amplifiers are divided into a first set and a second set, the first set of sense amplifiers being dedicated to performing sense amplification in memory read operations in any core bank and the second set of sense amplifiers being dedicated to performing sense amplification in memory modify operations in any core bank;
• data output circuitry connected to sense output signals generated by a first set of sense amplifiers;
• control circuitry for receiving input control signals and selectively controlling execution of memory read and memory modify operations on nonvolatile memory cells in any of the core banks, a memory read operation being capable of being performed in any core bank in which a memory modify operation is not being performed;
• and
• demultiplexing circuitry associated with each core bank and connected to addressed column lines therein, the demultiplexing circuitry selectively connecting an addressed column line to a sense amplifier in any of the first and second groups of sense amplifiers, based upon the type of memory operation being performed in the core bank in which the addressed column is located.

An electronics device, comprising:

• a processing element;
• and
• a nonvolatile memory device, coupled to the processing element, comprising:
• more than two core banks of nonvolatile memory cells, memory cells in each core bank being arranged in addressable rows and columns of nonvolatile memory cells, and each column of memory cells in a core bank being coupled to a distinct column line in the core bank;
• a plurality of address decode circuits, each address decode circuit being associated with a distinct core bank of nonvolatile memory cells and adapted to connect addressed memory cells to a plurality of column lines in the core bank of nonvolatile memory cells associated with the address decode circuit;
• a plurality of sense amplifiers coupled to the column lines in the core banks;
• data output circuitry connected to sense output signals generated by a first set of sense amplifiers;
• configuration circuitry, programmable or programmed, for maintaining information concerning grouping of the core banks into at least two core bank groups;
• and
• control circuitry, coupled to the configuration circuitry, for receiving input control signals and selectively controlling execution of memory read and memory modify operations on nonvolatile memory cells in any of the core banks, a memory read operation being capable of being performed in any core bank group in which a memory modify operation is not being performed.