Piggyback programming using an extended first pulse for multi-level cell flash memory designs
AssigneeAdvanced Micro Devices, Inc.
InventorAllan Parker
Life of this patent
Estimating the term…
Abstract
A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes generating a first programming pulse, generating a second programming pulse subsequent to the generating the first programming pulse, wherein the first programming pulse has a width that is greater than the second programming pulse and programming at least two of the 2N voltage levels with the first programming pulse.
Claims36
A method of programming a plurality of memory cells, wherein each of said memory cells has 2N voltage levels where N>1 and represents the number of bits stored within said memory cell, the method comprising:
- applying a first programming pulse to a first of said memory cells, wherein said first programming pulse comprises 2N−1 portions;
- applying a second programming pulse to said first of said memory cells subsequent to said first programming pulse, wherein said second programming pulse comprises 2N−1 portions;
- wherein said first of said memory cells is programmed during one of said portions of said first programming pulse and one of said portions of said second programming pulse;
- and
- wherein said first programming pulse has a width that is greater than said second programming pulse.
A method of programming an array of flash memory cells, wherein each of said flash memory cells has at least four voltage levels representing two or more bits stored within said flash memory cell, and wherein each of said flash memory cells comprises a drain connected to a bitline and a gate connected to a wordline, the method comprising:
- applying a first multi-step programming pulse to a wordline corresponding to a first of said flash memory cells and a wordline corresponding to a second of said flash memory cells,
- uninhibiting only a bitline corresponding to said first of said flash memory cells during a first step of said first multi-step programming pulse, wherein a first voltage level is programmed in said first of said flash memory cells;
- uninhibiting only a bitline corresponding to said second of said flash memory cells and said bitline corresponding to said first of said flash memory cells during a second step of said first multi-step programming pulse, wherein a second voltage level is programmed in said second of said flash memory cells;
- applying a second multi-step programming pulse to said wordline corresponding to said first of said flash memory cells and said wordline corresponding to said second of said flash memory cells;
- uninhibiting only said bitline corresponding to said first of said flash memory cells during a fist step of said second multi-step programming pulse, wherein said first voltage level is further programmed in said first of said flash memory cells;
- uninhibiting only said bitline corresponding to said second of said flash memory cells and said bitline corresponding to said first of said flash memory cells during a second step of said second multi-step programming pulse, wherein said second voltage level is further programmed in said second of said flash memory cells;
- and
- wherein said first multi-step programming pulse has a pulse width that is greater than said second multi-step programming pulse.
Dependencies are inferred from the claim text.