MRAM architecture and system
AssigneeMotorola, Inc.
InventorPeter K. Naji
Life of this patent
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Abstract
A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.
Claims4
A method of operating a magnetoresistive memory comprising the steps of:
- providing a macro portion of a magnetoresistive memory including a plurality of magnetoresistive memory cells arranged in rows and columns, the memory array including a reference column of magnetoresistive memory cells, a plurality of word/digit lines one each magnetically associated with each row of magnetoresistive memory cells, a plurality of bit lines one each magnetically associated with each column of magnetoresistive memory cells, and first and second current source/sinks attached to opposite ends of each of the plurality of bit lines;
- initializing all bit lines during a first time period and selecting a specific bit line and word/digit line during the first time period in response to the application of an address;
- and
- flowing program current through the selected word/digit lines and bit lines during a subsequent time period to store data in a magnetoresistive memory cell positioned at a junction of the selected bit line and word/digit line.
Dependencies are inferred from the claim text.