Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns
AssigneeHewlett-Packard Development Company, L.P.
InventorsRobert J Brooks, Alexander J Neudeck
Life of this patent
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Abstract
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Claims31
A method of reading and performing a logical operation on a column of a memory array, comprising:
- creating a first voltage differential between a first row-supply line and a second row-supply line;
- creating a second voltage differential between a third row-supply line and a fourth row-supply line;
- sensing a current on at least one column-supply line.
A method of reading and performing a logical operation on a column of a memory array, comprising:
- driving a first voltage differential between a first supply line and a second supply line wherein said first supply line is connected to a first inverter in a plurality cells of a first row and said second supply line is connected to a second inverter in said plurality of cells of said row thereby causing a first current to flow between said first supply line and at least a third supply line when a cell of said plurality of cells in said row is in a first state;
- driving a second voltage differential between a fourth supply line and a fifth supply line wherein said fourth supply line is connected to said first inverter in a plurality cells of a second row and said fifth supply line is connected to said second inverter in said plurality of cells of said row thereby causing a second current to flow between said fourth supply line and at least said third supply line when a cell of said plurality of cells in said second row is in said first state;
- detecting at least one of said first current and said second current.
A method of reading and performing a logical operation on a column of a memory array, comprising:
- supplying a first supply line, a second supply line, a third supply line, and a fourth supply line with an operating voltage;
- supplying a voltage differential between said first supply line and said second supply line that is at least a threshold voltage of a field-effect transistor in magnitude thereby causing at least a first cell to conduct a detectable amount of current between said first supply line and a fifth supply line;
- supplying said voltage differential between said third supply line and said fourth supply line thereby causing at least a second cell to conduct a detectable amount of current between said third supply line and said fifth supply line;
- and,
- detecting said detectable amount of current.
A method of reading and performing a logical operation on a row of a memory array, comprising:
- creating a first voltage differential between a first column-supply line and a second column-supply line;
- creating a second voltage differential between a third column-supply line and a fourth column-supply line;
- sensing a current on at least one row-supply line.
A method of reading and performing a logical operation on a row of a memory array, comprising:
- driving a first voltage differential between a first supply line and a second supply line wherein said first supply line is connected to a first inverter in a plurality cells of a first column and said second supply line is connected to a second inverter in said plurality of cells of said column thereby causing a first current to flow between said first supply line and at least a third supply line when a cell of said plurality of cells in said column is in a first state;
- driving a second voltage differential between a fourth supply line and a fifth supply line wherein said fourth supply line is connected to said first inverter in a plurality cells of a second column and said fifth supply line is connected to said second inverter in said plurality of cells of said column thereby causing a second current to flow between said fourth supply line and at least said third supply line when a cell of said plurality of cells in said second column is in said first state;
- detecting at least one of said first current flow and said second current flow.
Dependencies are inferred from the claim text.