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US 6,552,923 B2Granted
SRAM with write-back on read
AssigneeTexas Instruments Incorporated
InventorTheodore W. Houston
Life of this patent
Estimating the term…
Abstract
A data storage cell that is stable on standby but upsets on read. Standby stability is achieved without read and restore. In one embodiment, the leakage current is balanced by manipulating the transistor widths and lengths, making the subthreshold current of the pass transistor greater than that of the drive transistor. A write-back during the read cycle compensates for the read upset.
Claims6
A memory subsystem, comprising:
- a 4T memory cell consisting essentially of two pass transistors with a first W/L ratio and two drive transistors with a second W/L ratio wherein said first W/L ratio is greater than said second W/L ratio;
- and
- said 4T memory cell upsets on read.
A method of operating a memory subsystem, comprising:
- providing a 4T memory cell consisting essentially of two pass transistors with a first W/L ratio and two drive transistors with a second W/L ratio wherein said first W/L ratio is greater than said second W/L ratio;
- performing a read operation which upsets voltage values existing on said 4T memory cell before said read operation;
- and
- performing a write back operation after said read operation wherein said voltage values existing on said 4T memory cell before said read operation are restored on said 4T memory cell.
1 more element
A memory subsystem, comprising:
- a 4T memory cell consisting essentially of two pass transistors with a first leakage current and two drive transistors with a second leakage current wherein said first leakage current is greater than said second leakage current;
- and
- said 4T memory cell upsets on read.
Dependencies are inferred from the claim text.