Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a sense amplifier and a bit line pair

A ferroelectric memory comprising:

• a memory cell unit comprising a plurality of memory cells in each of which a first electrode of a ferroelectric capacitor is electrically connected to a source of a first transistor and a second electrode is electrically connected to a drain of said first transistor;
• a plurality of word lines each of which is electrically connected to a gate of said first transistor;
• a plate line electrically connected to the first electrode of said memory cell unit;
• a first bit line electrically connected to the second electrode of said memory cell unit via a block select transistor;
• a sense amplifier to compare and amplify voltages of a bit line pair of said first bit line and its complementary second bit line;
• a pair of second transistors each of which receives a voltage of said bit line pair at each control electrode, a pair of input/output nodes of said sense amplifier are electrically connected to each pair of electrodes of said second transistors;
• and
• a pair of third transistors each of which is inserted between said pair of said input/output nodes of the sense amplifier and the bit line pair, and controlled to convey data which was amplified by said sense amplifier to said bit line pair by being turned on after a plate line voltage falls to 0V.