Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory

A circuit to simulate a polarization relaxation phenomenon of a ferroelectric memory, comprising:

• a MOS transistor, wherein a gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line;
• a ferroelectric capacitor, wherein a first electrode of the ferroelectric capacitor is coupled to a drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line;
• and
• a relaxation voltage source, wherein a first terminal of the relaxation voltage source is coupled to the drain of the MOS transistor and the second terminal of the relaxation voltage source is coupled to a ground.

A circuit to simulate a polarization relaxation phenomenon of a ferroelectric memory, comprising:

• a MOS transistor;
• a ferroelectric capacitor, wherein a first electrode of the ferroelectric capacitor is coupled to a drain of the MOS transistor and a second electrode of the ferroelectric capacitor receives a control voltage for operating the ferroelectric capacitor;
• a capacitor, wherein a first electrode of the capacitor is coupled to the drain of the MOS transistor;
• and
• a relaxation voltage source coupled to the capacitor.