Saving content addressable memory power through conditional comparisons

A content addressable memory array comprising:

• a plurality of memory sub-arrays, each of said sub-arrays including at least one memory cell;
• a matchline connected to each of said sub-arrays;
• a sinkline connected to each of said sub-arrays;
• and
• said sinkline and said matchline adapted to be set to a second voltage from a first voltage, said second voltage having a higher absolute value than said first voltage,
• wherein said second voltage appearing on said matchline and said first voltage appearing on said sinkline indicates a match between data within all of said sub-arrays and input data, and said second voltage appearing on said sinkline indicates a mismatch between data within any of said sub-arrays and said input data,
• wherein an invalid status within said valid memory cell maintains said sinkline at said second voltage,
• wherein a first of said sub-arrays having data different than said input data maintains said sinkline at said second voltage, and
• wherein said sinkline maintains said matchline at said second voltage while said sinkline is at said second voltage.

A content addressable memory array comprising:

• a plurality of memory sub-arrays, each of said sub-arrays including at least one memory cell;
• a matchline connected to each of said sub-arrays;
• a comparator having a first input connected to said matchline;
• a valid memory cell connected to a second input of said comparator;
• a sinkline output from said comparator;
• and
• said sinkline and said matchline adapted to be set to a second voltage from a first voltage;
• wherein said second voltage appearing on said matchline and said first voltage appearing on said sinkline indicates a match between data within all of said sub-arrays and input data, and said second voltage appearing on said sinkline indicates a mismatch between data within any of said sub-arrays and said input data.

A content addressable memory array comprising:

• a plurality of memory sub-arrays;
• a matchline connected to each of said sub-arrays;
• and
• a sinkline connected to each of said sub-arrays,
• wherein said sinkline and said matchline are adapted to be initially set to a second voltage from a first voltage and to be reset to said first voltage, each depending on results of comparing input data with data contained within said sub-arrays,
• wherein said second voltage has a higher absolute value than said first voltage, and
• wherein said matchline is prevented from discharging from said second voltage to said first voltage if said first voltage appears on said sinkline and one of said sub-arrays has data matching said input data.

A content addressable memory array comprising:

• a plurality of memory sub-arrays;
• a matchline connected to each of said sub-arrays;
• and
• a sinkline connected to each of said sub-arrays,
• wherein said sinkline and said matchline are adapted to be initially set to a second voltage from a first voltage and to be reset to said first voltage, each depending on results of comparing input data with data contained within said sub-arrays,
• wherein said second voltage has a higher absolute value than said first voltage,
• wherein a first of said sub-arrays having data different than said input data maintains said sinkline at said second voltage, and
• wherein said matchline is prevented from discharging from said second voltage to said first voltage while said sinkline is at said second voltage.