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US 6,552,887 B1Granted
Voltage dependent capacitor configuration for higher soft error rate tolerance
AssigneeIntel Corporation
InventorsTanay Karnik, Rajendran Nair, Vivek K. De
Life of this patent
Estimating the term…
Abstract
A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.
Claims25
An apparatus comprising:
- an integrated circuit node to conduct a signal;
- and
- an explicit capacitor that is compatible with fabrication steps used to build a MOS integrated circuit device, coupled to the node and having a capacitance that changes in response to noise to increase a soft error rate tolerance of the node.
An apparatus comprising:
- a signal node;
- and
- means for increasing a capacitance of said signal node for enabling the state stored on said node to be unaffected by noise, said means having a capacitance that increases in response to noise.
An apparatus comprising:
- a explicit capacitor having an adjustable capacitance that changes in response to noise;
- and
- a signal state stored on said capacitor,
- wherein the adjustable capacitance enables the state to be unaffected by noise, so that the state remains stored unchanged on the capacitor.
1 more element
An apparatus comprising:
- a explicit capacitor having a capacitance that changes in response to noise, said capacitor including
- a pMOS FET device to operate as a first capacitor to store a first charge;
- an nMOS FET device to operate as a second capacitor to store a second charge, the gates of the FETs are connected to a signal node to receive an input signal.
An apparatus comprising:
- a explicit capacitor having a capacitance that increases in response to noise, said capacitor including
- a p-substrate;
- an n-well located in the p-substrate;
- an n-type polysilicon gate above the n-well as one plate of the explicit capacitor;
- and
- an n-tap attached to the n-well as another plate of the explicit capacitor.
3 more elements
A method comprising:
- applying a signal to a node of an integrated circuit;
- and
- providing, via an on-chip structure, additional capacitance to the node in response to noise that tends to change a state of the signal on the node.
Dependencies are inferred from the claim text.