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US 6,552,708 B1Granted
Unit gain buffer
AssigneeIndustrial Technology Research Institute
InventorsBo-Wen Wang, Jun-Ren Shih, Shang-Li Chen
Life of this patent
Estimating the term…
Abstract
The present invention is related to a unit gain buffer of the driver circuit to drive the data line in the filed of LCD data driver, further to be preferably applied to the new TFT-LCD processing of low temperature poly-silicon. This invention is using the plurality of PMOS transistor connection to result in the almost same value between the Vout and Vin. There is no using of the feedback connection in this invention, so the using of the compensation capacitor can be avoided, furthermore the data driver layout area of the LCD driver can be reduced. This invention can improve the defect of the larger layout area result from the prior art.
Claims10
A unit gain buffer for reducing the layout area of the data driver in TFT-LCD panel, comprising:
- an input transistor M1 connected to a constant current source I1 via the source pole of M1, the gate pole of M1 being the input Vin of the unit gain buffer;
- a high bias transistor consisted of transistors M2 and M3 in series connection, the gate pole of M3 connected to Vin, the source pole of M2 connected to the constant current source I1, further the gate pole of M2 connected to the drain pole of M3 and with a constant current source I2;
- an output transistor M4 connected to a constant current source I3 via the drain pole of M4, the drain pole of M4 being the output Vout of the unit gain buffer and connected to the gate pole of M4, the source pole of M4 connected to the connection point A between M2 and M3;
- wherein, the voltage of point A is almost the same as the input Vin, there is only difference Vgs of M3 between the point A and Vin, that is Vin=VA−DVgs3, by using the M4 to make the Vout=VA+Vgs4 and Vgs3 is same as Vgs4, then Vout is almost the same as Vin;
- and
- when the Vout and Vin are all in high level, then the Vin is changed into low level suddenly, the M1 is changed into linear region immediately and produces a large current, the large current flows into the drain pole of M4 via the N-well contact to output, that is the large current is from drain pole into body pole to form a current path, and this is the same as M2 to form a current path so the M2 and M4 produce a discharging current path.
3 more elements
A unit gain buffer for reducing the layout area of the data driver in TFT-LCD panel, comprising:
- an input transistor M1 connected to a constant current source I1 via the source pole of M1, the gate pole, of M1 being the input Vin of the unit gain buffer;
- a high bias transistor consisted of transistors M2 and M3 in series connection, the gate pole of M3 connected to Vin, the source pole of M2 connected to the constant current source I1, further the gate pole of M2 connected to the drain pole of M3 and with a constant current source I2;
- an output transistor M4 connected to a constant current source I3 via the drain pole of M4, the drain pole of M4 being the output Vout of the unit gain buffer and connected to the gate pole of M4, the source pole of M4 connected to the connection point A between M2 and M3;
- wherein, the voltage of point A is almost the same as the input Vin, there is only difference Vgs of M3 between the point A and Vin, that is Vin=VA−DVgs3, by using the M4 to make the Vout=VA+Vgs4 and Vgs3 is same as Vgs4, then Vout is almost the same as Vin;
- when the Vout and Vin are all in high level, then the Vin is changed into low level suddenly, there is only constant current source I3 provided discharge mainly, and the M4 leakage current is also to form a discharge current path in the low temperature poly-silicon TFT fabrication process.
2 more elements
A data driver of TFT-LCD panel to drive a data line, comprising:
- a digital-to-analog converter receiving the digital transmission signals transferred into analog signals to drive the pixel;
- a unit gain buffer connected to said digital-to-analog converter and coupled to the data line of TFT-LCD panel to drive the data line, comprising:
- an input transistor M1 connected to a constant current source I1 via the source pole of M1, the gate pole of M1 being the input Vin of the unit gain buffer, which is a PMOS transistor;
- a high bias transistor consisted of two PMOS transistors M2 and M3 in series connection, the gate pole of M3 connected to Vin, the source pole of M2 connected to the constant current source I1, further the gate pole of M2 connected to the drain pole of M3 and with a constant current source I2;
- an output transistor M4 connected to a constant current source I3 via the drain pole of M4, the drain pole of M4 being the output Vout of the unit gain buffer and connected to the gate pole of M4, the source pole of M4 connected to the connection point A between M2 and M3, and M4 is a PMOS transistor;
- wherein, the voltage of point A is almost the same as the input Vin, there is only difference Vgs of M3 between the point A and Vin, that is Vin=VA−DVgs3, by using the M4 to make the Vout=VA+Vgs4 and Vgs3 is same as Vgs4, then Vout is almost the same as Vin;
- and
- wherein said Vout and Vin of the unit gain buffer are all in high level, then the Vin is changed into low level suddenly, the M1 is changed into linear region immediately and produces a large current, the large current flows into the drain pole of M4 via the N-well contact to output, that is the large current is from drain pole into body pole to form a current path, and this is the same as M2 to form a current path, so the M2 and M4 produce a discharging current path.
5 more elements
Dependencies are inferred from the claim text.