Multi-channel clock recovery circuit

A digital clock recovery method, comprising the steps of:

• generating half-speed quadrature clocks operating at half speed of an incoming data rate of a data channel, wherein a first pair of the half-speed quadrature clocks having an inverse phase relationship are capable of registering input data of the data channel at a center of an eye of the input data, and wherein a second pair of the half-speed quadrature clocks having an inverse phase relationship and a phase difference of 90° and 270° relative to the first pair of half-speed quadrature clocks, respectively, have transitions occurring in a middle of transition regions of the input data eye, wherein the phases of the half-speed quadrature clocks span two data eyes of the input data, and wherein in a given half-speed recovered clock cycle there can be as many as two transitions of the input data;
• and
• synchronizing the half-speed quadrature clocks and the input data of the data channel, the synchronization step further comprising the steps of:
• analyzing a position of each of the data transitions of the input data relative to each of the four phases of the half-speed quadrature clocks, and
• comparing a first sum of transitions of the input data occurring between quadrature phases to a second sum of transitions of the input data occurring between quadrature phases, wherein a comparison result is indicative of the relative phase between the half-speed quadrature clocks and the input data.

A multiple channel clock recovery circuit for generating half-speed quadrature clocks from input data of each of the multiple channels, the multiple channel clock recovery circuit comprising:

• a voltage controlled oscillator outputting a plurality of half-speed reference clocks having a half-speed frequency relative to the input data;
• and
• a plurality of clock recovery circuits, each of the plurality of clock recovery circuits including a phase locked loop circuit receiving the input data of one of the multiple channels and having a phase multiplexor, the phase multiplexor receiving the plurality of half-speed reference clocks and being controlled to output the four half-speed quadrature clocks having relative phases of 0°, 90°, 180°, and 270° relative to the eye of the input data, wherein the four half-speed recovered clocks are used by the phase locked loop as feedback reference clocks, and wherein the phase locked loop comprises:
• a digital phase detector receiving the input data and the half-speed quadrature clocks, the digital phase detector comparing the phase of the input data to the phase of the half-speed quadrature clocks and generating an error signal indicating a difference in phase between the phase of the input data and the phase of the half-speed quadrature clocks;
• a digital filter receiving and filtering the error signal to generate a filtered error signal;
• and
• a phase store having a phase counter for storing a current phase and having output logic for generating a plurality of control signals, the plurality of control signals corresponding to the current phase and controlling the phase multiplexor to select the four half-speed quadrature clocks corresponding to the current phase, the filtered error signal causing the phase counter to increment when the half-speed quadrature clocks lag the phase of the input data and decrement when the half-speed quadrature clocks lead the phase of the input data.