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US 6,552,616 B1Granted
Asynchronous phase detector for a PLD independent of timing requirements
AssigneeCisco Technology, Inc.
InventorsDavid Lai, Eugene Wang
Life of this patent
Estimating the term…
Abstract
An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.
Claims21
An apparatus, comprising:
- a first flip-flop having an output and a control input;
- a second flip-flop having an output and a control input;
- a first logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the first logic gate having an output, wherein the first logic gate is a NOR gate;
- and
- a latch having a control input coupled to the output of the logic gate, the latch having an output coupled to the control inputs of the first and second flip-flops, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.
2 more elements
A method, comprising:
- receiving a first output from a first flip-flop by a NOR gate;
- receiving a second output from a second flip-flop by the NOR gate;
- generating a first value for a reset signal by the NOR gate based on the first and second outputs;
- detecting a state change on the first and second outputs;
- and
- holding the first value of the reset signal until the state change is detected on both the first and second outputs.
3 more elements
An apparatus, comprising:
- a phase detector;
- and
- means for resetting an output of said phase detector independent of routing path lengths between components internal to said phase detector, wherein the means for resetting comprises a latch disposed between a NOR gate and first and second flip-flops to receive a reset signal and hold the reset signal until both the first and second flip-flops are reset.
A phase locked loop, comprising:
- a voltage controlled oscillator;
- and
- a phase detector coupled to the voltage controlled oscillator, the phase detector comprising:
- a first flip-flop having an output and a control input;
- a second flip-flop having an output and a control input;
- a first logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the first logic gate having an output, wherein the first logic gate is a NOR gate;
- and
- a latch having a control input coupled to the output of the logic gate, the latch having an output coupled to the control inputs of the first and second flip-flops, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.
5 more elements
A switch, comprising:
- a framer;
- and
- a phase locked loop coupled to the framer, the phase locked loop comprising:
- a voltage controlled oscillator;
- and
- a phase detector coupled to the voltage controlled oscillator, the phase detector comprising:
- a first flip-flop having an output and a control input;
- a second flip-flop having an output and a control input;
- a first logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the first logic gate having an output, wherein the first logic gate is a NOR gate;
- and
- a latch having a control input coupled to the output of the logic gate, the latch having an output coupled to the control inputs of the first and second flip-flops, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.
8 more elements
Dependencies are inferred from the claim text.