Power down circuit detecting duty cycle of input signal

A power-saving chip comprising:

• a clock input that receives a clock from a system power controller, the clock being stopped when the system power controller places the power-saving chip into an idle mode;
• a clock buffer that receives the clock from the clock input and drives a filter input;
• a filter that receives the clock on the filter input from the clock buffer and generates a filtered clock;
• a first comparator that receives the filtered clock from the filter and compares the filtered clock to a first reference and generates a first output;
• a second comparator that receives the filtered clock from the filter and compares the filtered clock to a second reference and generates a second output;
• and
• combining logic that receives the first output from the first comparator and the second output from the second comparator and generates an power-down signal;
• wherein the power-down signal is activated to power-down at least part of the power-saving chip when the filtered clock exceeds the first reference or the filtered clock is under the second reference, but the power-down signal is not activated when the filtered clock is between the first and second references, whereby power is reduced when the clock's duty cycle is outside of a range determined by the first and second references.

A duty-cycle-detecting power-down circuit comprising:

• clock input means for receiving a clock that is stopped to signal a power-saving mode;
• filter means for averaging the clock over several clock periods to produce an average clock voltage;
• first compare means, receiving the average clock voltage from the filter means and receiving a first reference voltage, for activating an upper-limit signal when the average clock voltage exceeds the first reference voltage;
• a second compare means, receiving the average clock voltage from the filter means and receiving a second reference voltage, for activating a lower-limit signal when the average clock voltage is below the second reference voltage;
• and
• logic means, receiving the upper-limit signal from the first compare means and the lower-limit signal from the second compare means, for activating a power-down signal when the lower-limit signal or the upper-limit signal is activated, whereby the power-down signal is generated when the average clock voltage is above an upper limit or below a lower limit.