Word line testability improvement
AssigneeSTMicroelectronics S.r.l.
InventorsWilliam Barnes, Paul Hammond
Life of this patent
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Abstract
The present invention proposes a method of disabling a particular decoder output during scan-mode testing without impacting the critical path during either scan-mode or the normal mode of operation. During scan-mode testing a known bit stream may be programmed into latches and provides a means of functional testing the device in question. Three embodiments are used in conjunction with a disable driver to pull an intermediate node HIGH. The intermediate node is inverted by an output driver, which disables the relevant decoder output. The first embodiment involves using a full CMOS gate, the second embodiment uses ratio logic and the third uses a weak pull-up resistor.
Claims12
A decoder for activating one of a plurality of output lines depending on a binary address received on a plurality of input lines each providing a respective inverted and non-inverted input which are synchronised by a decode signal, the decoder having a plurality of identical circuits each for driving one of said output lines, each circuit comprising:
- a plurality of serially connected switching elements between a first node and a second node, each switching element receiving an input from at least one of said respective inverted or non-inverted input lines;
- pull-up means for pulling said first node to a high potential;
- an output driver connecting said first node to said output line;
- and
- a disable driver for driving said second node to a low or a high potential depending on the decoder's mode of operation.
A method for operating a decoder for activating one of a plurality of output lines depending on a binary address received on a plurality of input lines each having an inverted and a non-inverted input which are synchronised by a decode signal, the decoder having a plurality of identical circuits each for driving one of said output lines, wherein the method for operating each circuit comprises:
- applying said respective inverted or non-inverted inputs to a plurality of serially connected stacked switching elements between a first node and a second node;
- pulling said first node to a high potential using pull-up means;
- driving said output line with an output driver connected to said first node;
- and
- driving said second node to a high or low potential with a disable driver depending on the decoder's mode of operation.
Dependencies are inferred from the claim text.