Low power dynamic logic gate with full voltage swing operation

A method of controlling a precharge path in a logic circuit that includes a discharge path connected between an output node and a clock line and including one or more transistors for implementing a logic function of the logic circuit, the precharge path including a PMOS transistor having a source connected to the clock line and a drain connected to the output node, the clock line carrying a clock signal cycling between a first voltage and a second voltage, the method comprising:

• disabling the precharge path during first voltage of the clock signal by providing the first voltage to the source of the PMOS transistor;
• and
• enabling the precharge path during the second voltage of the clock signal by providing the second voltage to the source of the PMOS transistor and providing to a gate of the PMOS transistor a voltage having a range of approximately a NMOS transistor threshold voltage above the first voltage of the clock line to one PMOS transistor threshold voltage below the second voltage of the clock line.