System and method for reducing leakage current in dynamic circuits with low threshold voltage transistors
AssigneeTexas Instruments Incorporated
InventorJames B. Barton
Life of this patent
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Abstract
A reduced-leakage current dynamic circuit (10) is disclosed that includes a logic circuit (30), a pre-charge transistor (32), and a standby transistor (40). The logic circuit (30) is coupled to an internal output node (50). The logic circuit (30) includes a plurality of logic transistors (60 and 62) having a low threshold voltage. The pre-charge transistor (32) is coupled to the internal output node (50). The pre-charge transistor (32) is operable to provide a pre-charge voltage at the internal output node (50) and has a standard threshold voltage. The standby transistor (40) is coupled to the internal output node (50). The standby transistor (40) is operable to provide a standby voltage at the internal output node (50).
Claims9
A reduced-leakage current dynamic circuit having an active mode and a standby mode and including transistors having a standard threshold voltage and transistors having a low threshold voltage lower than the standard threshold voltage, comprising:
- a logic circuit coupled between an internal output node and ground, the logic circuit comprising a plurality of logic transistors each having the low threshold voltage, the logic circuit conditionally coupling the internal output node to the reference dependent upon logic signals received by the plurality of logic transistors;
- a pre-charge transistor coupled to the internal output node and a pre-charge voltage, the pre-charge transistor having the standard threshold voltage, the pre-charge transistor receiving a clock signal, the clock signal in the active mode alternating between a first voltage causing the pre-charge transistor to couple the internal node of the pre-charge voltage and a second voltage causing the pre-charge transistor to isolate the internal node from the pre-charge voltage, the clock signal in the standby mode maintaining the second voltage isolating the internal node from the pre-charge voltage;
- and
- a standby transistor coupled between the internal output node and ground the standby transistor the standby transistor receiving a standby signal, the standby signal in the active move causing the standby transistor to isolate the internal output node from ground, the standby signal in the active mode causing the standby transistor to couple the internal output node to ground.
A method for designing an optimized reduced-leakage current dynamic circuit, the dynamic circuit comprising a plurality of sub-circuits, each sub-circuit having an active mode and a standby mode, each sub-circuit having an internal output node, a pre-charge transistor having a standard threshold voltage, a source-drain path connected between a power voltage source and the internal output node and a gate receiving a clock signal and a conditional discharge logic circuit connected between the internal output node and ground including at least one transistor having a low threshold voltage lower than the standard threshold voltage, the conditional logic circuit receiving at least one input and conditionally providing a discharge path between the internal output node and ground dependent on a logic state of the at least one input, the clock signal in the active mode cycling between a voltage causing the pre-charge transistor to conduct and a second voltage causing the pre-charge transistor to be cut off, the clock signal in the standby mode maintaining the second voltage cutting off the pre-charge transistor, the method comprising:
- identifying a set of primary input nodes for receiving inputs for the circuit, each primary input node associated with a sub-circuit;
- providing a standby transistor for each sub-circuit associated with a primary input node, the standby transistor having a source-drain path coupled between the internal output node of the sub-circuit and ground, the standby transistor having a gate receiving a standby signal, the standby signal in the active mode causing the standby transistor to be cut off and in the standby mode causing the standby transistor to conduct.
A method for reducing leakage current in a dynamic logic circuit having an active mode and a standby mode, the dynamic logic circuit having at least one transistor with a standard threshold voltage and at least one transistor with a low threshold voltage lower than the standard threshold voltage, the method comprising the steps of:
- in the active mode
- charging an internal output node to a pre-charge voltage via a pre-charge transistor having the standard threshold voltage;
- conditionally discharging the internal output node to ground via a logic block corresponding to a logic state of at least one input, the logic block including at least one logic transistor, each logic transistor having the low threshold voltage;
- in the standby mode
- cutting off the pre-charge transistor preventing charging the internal node to the pre-charge voltage;
- and
- discharging the internal output node to ground via a standby transistor having the standard threshold voltage.
Dependencies are inferred from the claim text.