Back to results
US 6,552,572 B1Granted
Clock gating cell for use in a cell library
AssigneeLSI Logic Corporation
InventorsCyrus C. Cheung, Keith D. Au
Life of this patent
Estimating the term…
Abstract
A clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.
Claims18
A clock gating cell, comprising:
- gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively;
- and
- a gated clock signal output configured to generate a gated clock signal that is a function of states of said gate enable and clock signals, said clock gating cell treated as an atomic entity in a cell library.
A method of manufacturing a clock gating cell, comprising:
- defining gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively;
- and
- defining a gated clock signal output configured to generate a gated clock signal that is a function of states of said gate enable and clock signals, said clock gating cell treated as an atomic entity in a cell library.
A clock gating cell, comprising:
- a latch configured to receive gate enable clock input signals and derive a latch signal therefrom;
- and
- combinatorial logic, coupled to said latch, configured to receive said latch and clock input signals and generate a gated clock signal therefrom, said latch and said combinatorial logic treated as an atomic entity in a cell library.
Dependencies are inferred from the claim text.