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US 6,552,570 B2Granted
Input circuit with non-delayed time blanking
AssigneeIntel Corporation
InventorsGregory F. Taylor, Chi-Yeu Chao
Life of this patent
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Abstract
An input circuit that receives an input signal and generates an output signal as a function of the input signal includes a latching circuit and a time blanking circuit. The latching circuit detects a transition of the input signal and causes a corresponding transition of the output signal. The time blanking circuit prevents the output signal from transitioning again for a predetermined period. This period begins with essentially no delay from the transition of the output signal, which can reduce the input circuit's sensitivity to high frequency noise that may be present on transitions of the input signal.
Claims30
A circuit, comprising:
- a first RS latch having a S terminal and a R terminal, the first RS latch to receive an input signal at its S terminal circuit;
- a second RS latch having a S terminal and a R terminal, the second RS latch to receive a complement of the input signal at its S terminal;
- a multiplexer, coupled to the first and second RS latches, to select an output signal from output signals from the first and second RS latches;
- and
- a delay circuit, coupled to the multiplexer and the first and second RS latches, to receive the output signal selected by the multiplexer and to provide a delayed version of the selected output signal to the second RS latch at its R terminal.
2 more elements
A circuit, comprising:
- latching means for detecting a transition of the input signal and to generate a corresponding transition of an output signal;
- and
- time blanking means, coupled to the latching means, for preventing any subsequent transition of the output signal for a predetermined period that begins with essentially no delay from the corresponding transition of the output signal.
A circuit, comprising:
- a first RS latch circuit having a first input lead, a second input lead and an output lead, the first input lead of the first RS latch circuit to receive an input signal;
- a second RS latch circuit having a first input lead, a second input lead and an output lead, the first input lead of the second RS latch circuit to receive the input signal;
- a
- multiplexer having a first input lead, a second input lead, a control lead and an output lead, the first and second input leads of the multiplexer being respectively coupled to the output leads of the first and second RS latch circuits;
- and
- a delay circuit having an input lead coupled to the output lead of the multiplexer and having an output lead coupled to the second input leads of the first and second RS latch circuits, the delay circuit to provide a delayed version of a signal received via the output lead of the multiplexer.
3 more elements
A method, comprising:
- monitoring an input signal;
- detecting a transition of the input signal;
- causing a transition of an output signal in response to the transition of the input signal;
- and
- preventing any transitions of the output signal during a time blanking period that begins with essentially no delay from the transition of the output signal.
2 more elements
An apparatus, comprising:
- means for monitoring an input signal;
- means for detecting a transition of the input signal;
- means for causing a transition of an output signal in response to the transition of the input signal;
- and
- means for preventing any transitions of the output signal during a time blanking period that begins with essentially no delay from the transition of the output signal.
2 more elements
A processor, comprising:
- an input circuit to generate an output signal as a function of an input signal, the input circuit comprising:
- a first RS latch circuit having a first input lead, a second input lead and an output lead, the first input lead of the first RS latch circuit to receive the input signal;
- a second RS latch circuit having a first input lead, a second input lead and an output lead, the first input lead of the second RS latch circuit to receive the input signal;
- a multiplexer having a first input lead, a second input lead, and an output lead, the first and second input leads of the multiplexer being respectively coupled to the output leads of the first and second RS latch circuits;
- and
- a delay circuit having an input lead coupled to the output lead of the multiplexer and having an output lead coupled to the second input leads of the first and second RS latch circuits and to a control lead of the multiplexer, the delay circuit to provide a delayed version of a signal received via the output lead of the multiplexer.
3 more elements
Dependencies are inferred from the claim text.