Wafer map display apparatus and method for semiconductor test system
AssigneeAdvantest Corporation
InventorMitsue Nanbu
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Abstract
A wafer map display apparatus and method for displaying an entire image of a semiconductor wafer and IC chips therein with an optimal display size within a specified window size. The wafer map display apparatus acquires window size information for displaying a wafer map of a semiconductor wafer under test in a specified window, and calculates a chip display size every time when test results and XY address data of an IC chip that has been tested is received with use of all of XY address data of IC chips that have been tested, and renews the wafer map display based on the newest chip display size, thereby displaying all of the IC chips that have been tested and an overall semiconductor wafer under test with an optimum size within the specified window.
Claims4
A method of displaying a wafer map which is an image of IC chips on a semiconductor wafer based on test results from a semiconductor test system controlled by a workstation, comprising the following steps of:
- acquiring window size information from a window managing system in the workstation for displaying the wafer map of a semiconductor wafer under test in a specified window of a display screen;
- calculating a chip display size every time when XY address data of an IC chip that has been tested is received from the semiconductor test system with use of all of XY address data of all of IC chips that have been tested up to present and the window size information;
- and
- renewing the wafer map display based on the newest chip display size determined by the step of calculating the chip display size, thereby displaying all of the IC chips that have been tested and an overall semiconductor wafer under test with a maximum available size within the specified window.
Dependencies are inferred from the claim text.