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US 6,552,420 B1Granted
Redundant pinout configuration for signal enhancement in IC packages
AssigneeMicron Technology, Inc.
InventorDavid J. Corisis
Life of this patent
Estimating the term…
Abstract
A semiconductor device assembly package includes a semiconductor device having components thereon which are generic to a variety of applications by manipulation of the pinout configuration. The lead frame includes redundant leads for connection to the semiconductor device, as desired. The semiconductor device may include redundant wire bond pads, each redundant pair including one pad on a lateral edge and one pad on a non-lateral edge of the die. In applications requiring less than all of the available leads, the pinout configuration of the leadframe is adjusted to use the extra space from unused NC leads and missing pins for providing wider, shorter leads with reduced inductance, and wider paddle arms for reduced bending and breakage.
Claims37
A semiconductor device assembly, comprising:
- a semiconductor device having opposing lateral edges and opposing non-lateral edges, said semiconductor device having a plurality of bond pads thereon, said plurality of bond pads comprising at least one redundant bond pad located along said non-lateral edge of said semiconductor device, said at least one redundant bond pad being a duplicate of an unconnected bond pad located along one of said opposing lateral edges;
- and
- a lead frame having a plurality of leads thereon, at least two leads bonded to said plurality of bond pads, one lead of said at least two leads is bonded to said at least one redundant bond pad, and the other lead of said at least two leads is bonded to a non-redundant bond pad, said one lead bonded to said at least one redundant bond pad having a length shorter than the other lead of said at least two leads to provide low inductance in the semiconductor device assembly.
A semiconductor device assembly, comprising:
- a semiconductor device having opposing lateral edges and opposing non-lateral edges, said semiconductor device having a plurality of bond pads thereon, said plurality of bond pads comprising at least one redundant bond pad located along said non-lateral edge of said semiconductor device, said at least one redundant bond pad being a duplicate of an unconnected bond pad located along one of said opposing lateral edges;
- and
- a lead frame having a plurality of leads thereon, at least two leads bonded to said plurality of bond pads, one lead of said at least two leads is bonded to said at least one redundant bond pad, and the other lead of said at least two leads is bonded to a non-redundant bond pad, said one lead bonded to said at least one redundant bond pad having a width thereof greater than a width of the other lead of said at least two leads to provide low inductance in the semiconductor device assembly.
A semiconductor device assembly, comprising:
- a semiconductor device having opposing lateral edges and opposing non-lateral edges, said semiconductor device having a plurality of bond pads thereon, at least two bond pads of the plurality of bond pads being redundant bond pads, said redundant bond pads located along said non-lateral edges of said semiconductor device, said redundant bond pads being duplicates of unconnected bond pads located along one of said opposing lateral edges;
- and
- a lead frame having a plurality of leads thereon, at least two leads bonded to said plurality of bond pads, one lead of said at least two leads is bonded to one of said at least two redundant bond pads, and the other lead of said at least two leads is bonded to a non-redundant bond pad, said one lead bonded to said one of said at least two redundant bond pads having a length shorter than the other lead of said at least two leads to provide low inductance in the semiconductor device assembly.
A semiconductor device assembly, comprising:
- a semiconductor device having a plurality of components, said semiconductor device having opposing lateral edges and opposing non-lateral edges, said semiconductor device having a plurality of conductive bond pads connected to said plurality of components, a portion of said plurality of bond pads provided in duplicate whereby said duplicate bond pads comprise redundant bond pads selectable for wire bonding, said redundant bond pads are located along said opposing non-lateral edges of the semiconductor device, said redundant bond pads being duplicates of unconnected bond pads located along one of said opposing lateral edges;
- a lead frame formed having a plurality of leads thereon, at least two-leads of said plurality of leads, one lead of said at least two leads for connecting to at least one said redundant bond pad of the plurality of bond pads of the semiconductor device, and the other lead of said at least two leads for connecting to a non-redundant bond pad, said one lead of said at least two leads of said plurality of leads being shorter than the other lead of said at least two leads to provide low inductance in the semiconductor device assembly;
- at least one wire bond extending between said shorter lead of said at least two leads of said plurality of leads of said lead frame and at least one said redundant bond pad of said semiconductor device;
- and
- a package enclosing said semiconductor device and a portion of said lead frame.
2 more elements
A semiconductor device assembly, comprising:
- a semiconductor device having a plurality of components, said semiconductor device having opposing lateral edges and opposing non-lateral edges, said semiconductor device having a plurality of conductive bond pads connected to said plurality of components, a portion of said plurality of bond pads provided in duplicate whereby said duplicate bond pads comprise redundant bond pads selectable for wire bonding, said redundant bond pads located along said opposing non-lateral edges of the semiconductor device, said redundant bond pads being duplicates of unconnected bond pads located along one of said opposing lateral edges;
- and
- a lead frame formed having a plurality of leads thereon, a first portion of the plurality of leads terminating adjacent the opposing lateral edges of the semiconductor device and having a first length and a second portion of the plurality of leads terminating adjacent the opposing non-lateral edges of the semiconductor device and having a second length longer than the first length, a width of the first portion of the plurality of leads being at least substantially the same as a width of the second portion of the plurality of leads to provide low inductance in the semiconductor device assembly.
Dependencies are inferred from the claim text.