US 6,552,410 B1 · Programmable antifuse interfacing a programmable logic and a dedicated device

Abstract

A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable and dedicated devices or through the interface and around the periphery of only one of the programmable and dedicated devices.

Claims13

Dependent claims

An apparatus comprising:

programmable logic;
a dedicated device and an interface disposed between said dedicated device and said programmable logic, said interface comprising an array of programmable antifuses.

An apparatus comprising programmable logic coupled to a dedicated device by an interface, said interface comprising:

a plurality of first conductors from said programmable logic to said dedicated device;
a plurality of second conductors from said dedicated device to said programmable logic;
buffers coupled to said first conductors and said second conductors;
a testing circuit coupled to each buffer, said testing circuit comprising:
a PMOS test transistor having a first terminal coupled to a voltage source, a second terminal coupled to an first output terminal, and a gate terminal coupled to the output terminal of said buffer;
an NMOS test transistor having a first terminal coupled to a ground source, a second terminal, and a gate terminal coupled to the output terminal of said buffer;
a weak detection circuit coupled to said testing circuit, said weak detection circuit comprising:
a first inverter including a first PMOS transistor and a first NMOS transistor, said first inverter having an input terminal and an output terminal, said input terminal coupled to a voltage source, and said output terminal coupled to said second terminal of said PMOS test transistor, said PMOS test transistor being larger than said first NMOS transistor in said first inverter;
a second inverter including a second PMOS transistor and a second NMOS transistor, said second inverter having an input terminal and an output terminal, said input terminal coupled to a ground source, and said output terminal coupled to said second terminal of said NMOS test transistor, said NMOS test transistor being larger than said first PMOS transistor in said second inverter.

6 more elements

Dependencies are inferred from the claim text.

Programmable antifuse interfacing a programmable logic and a dedicated device

Life of this patent

Programmable antifuse interfacing a programmable logic and a dedicated device

Life of this patent

Abstract

Claims13