US 6,552,409 B2 · Techniques for addressing cross-point diode memory arrays

Abstract

A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.

Claims19

Dependent claims

An integrated circuit structure comprising:

a first conductor layer having first and second conductor lines;
a second conductor layer having a third conductor line in a crossing relationship with the first and second conductor lines;
and
an intermediate layer having at least one semiconductor material interposed between the first and second conductor layers at least where the third conductor line crosses the first and second conductor lines so as to form first and second circuit elements through the intermediate layer at the respective crossing junctions of the first and second conductor lines with the third conductor line;
wherein the geometry of the first, second and/or third conductor lines at said crossing junctions being such that, upon application of a predetermined electrical signal through said first and second circuit connection elements, the first circuit connection element undergoes a permanent substantial change in resistance with respect to the second circuit connection element.

2 more elements

An integrated circuit structure comprising:

a first conductor layer having first and second conductor lines;
a second conductor layer having a third conductor line in a crossing relationship with the first and second conductor lines;
and
an intermediate layer having at least one semiconductor material interposed between the first and second conductor layers at least where the third conductor line crosses the first and second conductor lines so as to form first and second circuit elements through the intermediate layer at the respective crossing junctions of the first and second conductor lines with the third conductor line;
wherein the widths of the first, second and third conductor lines at said crossing junctions are specified so that upon application of a predetermined electrical signal through said first and second circuit elements, the first circuit element undergoes a permanent substantial change in resistance with respect to the second circuit element.

2 more elements

Dependencies are inferred from the claim text.

Techniques for addressing cross-point diode memory arrays

Life of this patent

Techniques for addressing cross-point diode memory arrays

Life of this patent

Abstract

Claims19