Loading patent…
AssigneeIBM Corporation
InventorsLouis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi
Estimating the term…
A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.
A memory system comprising a plurality of Thyristor-based Random Access Memory (“T-RAM”) cells having a planar cell structure, the T-RAM cells each having a lateral-gated thyristor device coupled to a transfer gate, and a common bitline contact region formed between transfer gates of adjacent T-RAM cells.
A Thyristor-based Random Access Memory (“T-RAM”) array comprising a planar cell structure, wherein the T-RAM array includes a plurality of T-RAM cells each having a lateral-gated thyristor device coupled to a transfer gate, and a common bitline contact region formed between transfer gates of adjacent T-RAM cells.
Dependencies are inferred from the claim text.