MOS integrated circuit with reduced ON resistance

An integrated circuit having a high voltage lateral DMOS, the high voltage lateral DMOS comprising:

• a substrate;
• a top layer of dielectric, the top layer having a first aperture and a second aperture, wherein the first aperture is laterally spaced a predetermined distance from the second aperture;
• a P− island formed in the substrate, wherein the P− island is positioned between the top layer and the substrate;
• a N+ drain contact formed in the P− island adjacent the first aperture of the top layer;
• a N+ source formed in the P− island adjacent the top layer, wherein at least a portion of the N+ source is positioned adjacent the second aperture of the top layer;
• a gate formed in the top layer adjacent the P− island, the gate is further positioned between the N+ source and the N+ drain contact;
• a N type first drain extension formed in the P− island, the first drain extension is positioned adjacent the top layer extending laterally from under the gate to the drain contact;
• and
• a N type second drain extension formed in the P− island, the second drain extension is positioned adjacent the top layer extending laterally from under the gate toward the N+ source, wherein a portion of the second drain extension overlaps the first drain extension under the gate.

A solid state relay integrated circuit comprising:

• a photo diode stack to drive a voltage having a first output and a second output;
• a first high voltage DMOS having a gate, source and drain, the gate of the first high voltage DMOS is coupled to the first output of the photo diode stack, the source of the first high voltage DMOS is coupled to the second output;
• a second high voltage DMOS having a gate, source and drain, the gate of the second high voltage DMOS is coupled to the first output of the photo diode stack, the source of the second high voltage DMOS is coupled to the second output of the photo diode stack;
• and
• wherein the first and second high voltage DMOS comprise,
• a top layer of dielectric, the top layer having a first aperture and a second aperture, wherein the first aperture is laterally spaced a predetermined distance from the second aperture,
• an island formed in a substrate doped with a low density of a first conductivity type, wherein the island is positioned between the top layer and the substrate,
• a drain contact formed in the island adjacent the first aperture in the top layer and doped with a high density of a second conductivity type,
• a source formed in the island adjacent the second aperture in the top layer and doped with a high density of a second conductivity type,
• a gate positioned under the top layer adjacent the island and between the source and the drain contact,
• a first drain extension of the second conductivity type formed in the island, the first drain extension is positioned adjacent the top layer extending laterally from under the gate to the drain contact, and
• a second drain extension of the second conductivity type formed in the island, the second drain extension is positioned adjacent the top layer extending laterally from under the gate to the source, wherein a portion of the second drain extension and a portion of the first drain extension overlap under the gate.