US 6,552,379 B2Granted

Semiconductor device and manufacturing method thereof

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorYukihiro Nagai

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Abstract

A semiconductor device with capacitors which have a structure wherein fluctuation in thickness does not occur, even in the case that a dielectric film of low coverage is used. The semiconductor device is provided with adjoining first and second capacitors, wherein the respective capacitor is provided with lower electrode, dielectric film which contacts the top surface of the lower electrode and which has peripheral sidewall surfaces that continue to the peripheral sidewall surfaces of the lower electrode, first upper electrode that contacts the top surface of the dielectric film and a second upper electrode that contacts the top surface of the first upper electrode and the semiconductor device is further provided with a partition insulating film which covers the sidewall surfaces of lower electrode and the dielectric layer between the capacitors so that the second upper electrode contacts the top surface of the partition insulating film.

Claims10

Dependent claims

A semiconductor device comprising first and second capacitors adjoining each other, the respective lower electrode of which is electrically connected to impurity region in a semiconductor substrate and, the respective upper electrode of which is electrically connected to an external wire,

wherein said first and second capacitors, respectively, comprises:
lower electrode which contacts the top surface of an insulating layer, formed on said semiconductor substrate, and the top surface of plug wire passing through said insulating layer;
dielectric film which contacts the top surfaces of said lower electrode and which have peripheral sidewall surfaces which continue to the peripheral sidewall surfaces of the lower electrode;
and
first upper electrode which contacts the top surfaces of said dielectric film and a second upper electrode which contact the top surface of said first upper electrode,
wherein said semiconductor device further comprises a partition insulating film between said first and said second capacitors which contacts the top surface of said insulating layer and which covers the sidewalls of said lower electrode and of said dielectric film, and
wherein said second upper electrode contacts the top surface of said partition insulating film.

4 more elements

A method of manufacturing a semiconductor device with a plurality of capacitors, the respective lower electrode of which is electrically connected to impurity region in a semiconductor substrate and the respective upper electrode of which is electrically connected to an external wire, comprising:

the step of forming a lower electrode layer which contacts the top surface of an insulating layer formed on said semiconductor substrate and of plug wire provided in the insulating layer;
the step of forming a dielectric layer on said lower electrode layer;
the step of forming a first upper electrode layer on said dielectric layer;
the step of forming a plurality of basic capacitor structures made of lower electrodes, dielectric films and first upper electrodes by patterning said lower electrode layer, said dielectric layer and said first upper electrode layer;
the step of forming an insulating layer so as to fill in gaps between said plurality of basic capacitor structures and so as to cover said first upper electrodes;
and
the step of removing an upper layer portion of said insulating layer so as to form partition insulating films which isolate said plurality of basic capacitor structures and, at the same time, of exposing said first upper electrodes.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/121,602Filed 15 Apr 2002
Priority: JP 2001-19296926 Jun 2001
Published: US 2002/0195631 A126 Dec 2002
Granted: 22 Apr 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 53/00
Ferroelectric ram [feram] devices comprising ferroelectric memory capacitors
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/312
Having a storage electrode stacked over the transistor: with a bit line higher than the capacitor
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region