Semiconductor memory device having plate lines and precharge circuits

A semiconductor memory device comprising:

• a semiconductor substrate;
• a memory cell array formed in said semiconductor substrate, said memory cell array including bit lines and word lines crossing each other and memory cells arranged at intersections of the bit lines and the word lines and each having a transistor and a capacitor, said capacitor including a first electrode constituted of an impurity diffusion layer formed along a side wall and a bottom of a trench continuously with an impurity diffusion layer of the transistor and serving as a storage node, said trench being formed on a major surface of said semiconductor substrate adjacent to the transistor of each of said memory cells;
• a capacitor insulation film formed in the trench;
• and a second electrode buried into the trench with the capacitor insulation film interposed therebetween;
• bit-line precharge-circuits formed in said semiconductor substrate, to precharge the bit-lines;
• a plate electrode serving as the second electrode of each capacitor of the memory cells and formed on an interlayer insulation film that covers both the transistor of the memory cells and the capacitor in the area where the memory cell array is formed;
• and
• a wiring layer electrically connected to the plate electrode and connected to the impurity diffusion layer in the area where the bit-line precharge circuits are formed, said impurity diffusion layer serving as a power supply terminal of the bit-line precharge circuits, and said wiring layer being connected to the impurity diffusion layer through a contact hole formed in the interlayer insulation film.

A semiconductor memory device comprising:

• a semiconductor substrate;
• a memory cell array formed in said semiconductor substrate, said memory cell array including bit lines and word lines crossing each other and memory cells arranged at intersections of the bit lines and the word lines and each having a transistor and a capacitor, said capacitor including an impurity diffusion layer serving as a first electrode and formed along a side wall and a bottom of a trench, said trench being formed on a major surface of said semiconductor substrate adjacent to the transistor of each of said memory cells;
• a capacitor insulation film formed in the trench;
• and a second electrode buried into the trench with the capacitor insulation film interposed therebetween and electrically connected to an impurity diffusion layer of the transistor to serve as a storage node;
• bit-line precharge circuits formed in said semiconductor substrate, to precharge the bit-lines;
• a plate electrode extending from an area where the memory cell array is formed to an area where the bit-line precharge circuits are formed, and being for applying a power supply potential to said bit-line precharge circuits, said plate electrode being formed of a buried diffusion layer arranged inside the semiconductor substrate and being electrically connected to the first electrode of the capacitor, said plate electrode being also connected to an impurity diffusion layer serving as the power supply terminal of the bit-line precharge circuits.

A semiconductor memory device comprising:

• bit lines;
• word lines crossing said bit lines;
• memory cells arranged at intersections of said bit lines and said word lines, said memory cells including a plurality of capacitors to which a plate electrode is connected in common;
• an insulation film formed on the plate electrode;
• a bit-line precharge circuit for precharging said bit lines;
• and
• a wiring layer formed on said insulation film and electrically connected to said plate electrode and a power supply terminal of said bit-line precharge circuit.

A semiconductor memory device comprising:

• bit lines;
• word lines crossing said bit lines;
• memory cells arranged at intersections of said bit lines and said word lines, said memory cells including a plurality of capacitors to which a plate electrode is connected in common;
• a first insulation film formed on the plate electrode;
• a bit-line precharge circuit for precharging said bit lines;
• a first wiring layer formed on said first insulation film along a direction crossing said bit lines, said first wiring layer being connected to said plate electrode through a first via hole located on said plate electrode of said first insulation film;
• a second wiring layer formed on said first insulation film along a direction crossing said bit lines, said second wiring layer being connected to a power supply terminal of said bit-line precharge circuit through a contact hole located on said bit-line precharge circuit of said first insulation film;
• a second insulation film formed on said first wiring layer, said second wiring layer, and said first insulation film;
• and
• a third wiring layer formed on said second insulation film along a direction which is equal to that of said bit lines, said third wiring layer being connected to said first wiring layer through a second via hole formed in said second insulation film and said second wiring layer through a third via hole formed in said second insulation film.