Process for device using partial SOI

A process for manufacturing a field effect transistor, comprising:

• providing a body of P+ silicon having left and right edges;
• on the P+ silicon body, epitaxially depositing a layer of P− silicon, having an upper surface, and forming thereon a first layer of silicon oxide;
• on said first layer of silicon oxide depositing a first layer of silicon nitride;
• on said fast layer of silicon nitride depositing a second layer of silicon oxide;
• patterning said second layer of silicon oxide to define a plurality of trenches that extend away from the right edge by a first amount and then, using said patterned second layer of silicon oxide as a hard mask, etching said layer of silicon nitride, said first layer of silicon oxide, and said P− silicon body to a first depth below said upper surface, thereby forming said plurality of trenches;
• depositing on all exposed surfaces a two-layer laminate that further comprises a third layer of silicon oxide on a second layer of silicon nitride;
• selectively removing said two-layer laminate from all horizontal surfaces;
• using said patterned second layer of silicon oxide and said two-layer laminate as a hard mask, further etching said silicon body to a second depth below said upper surface, thereby forming a plurality of trenches, each having sidewalls;
• thermally oxidizing all exposed silicon surfaces until oxide layers growing both inwards and outwards from said sidewalk meet, thereby forming a continuous layer of silicon oxide below said first trenches and parallel to said upper surface;
• removing said two layer laminate;
• then overfilling said first trenches with polysilicon;
• using said patterned second layer of silicon oxide as a hard mask, using a planarizing etch to remove all polysilicon that is on said hard mask and then overetching until said polysilicon and said upper surface are co-planar;
• then removing said hard mask;
• then forming a sinker of P+ silicon that attends away from the left edge by a second amount and downwards from said upper surface into the P+ body;
• forming a layer of N-silicon, having a thickness less than said depth, that extends away from the right edge by a third amount;
• through a mask, forming first and second areas of a layer of N+ silicon that has a thickness greater than said depth, the first area extending away from the right edge for a first width that is less than said third amount and the second area being adjacent to, and extending away from, the sinker for a second width whereby a gap is left between the first and second N+ areas;
• forming a layer of gate oxide over said gap and depositing a gate electrode over the gate oxide;
• forming a layer of a conductive material on said upper surface that contacts both the P+ sinker and the source region;
• and
• forming a drain electrode over the second N+ drain region.