Ultra-thin body SOI MOSFET and gate-last fabrication method

A method of fabricating a MOSFET transistor on an SOI wafer having extended source-drain silicide and a gate with high-k insulation which is created subsequent to source-drain silicide formation, comprising:

• depositing a layer of insulator over the silicon on a second silicon layer of SOI wafer;
• selective etching of the insulator layer and underlying silicon layer such that a silicon-insulator stack is created having a segment of insulation attached above a segment of silicon;
• depositing a second layer of amorphous silicon (a-Si) over the silicon-insulator stack;
• removing upper portions of the amorphous silicon (a-Si) to expose the segment of insulation;
• implanting source-drain dopants beneath the segment of insulation;
• annealing the substrate to recrystallize the silicon and to activate dopants;
• forming silicide within the upper portion of the remaining lower portion of the recrystallized silicon layer (a-Si);
• removing of the segment of insulation to create a gate cavity;
• depositing high-k dielectric insulation within the interior of the gate cavity;
• and
• forming a gate electrode, whereupon the remaining fabrication steps may be performed according to conventional MOSFET device fabrication methods.

A method of fabricating ultra-thin body MOSFET transistor on an SOI wafer with a gate-last process, comprising:

• patterning dummy gate stacks on an SOI wafer that have a segment of deposited insulation stacked over a segment of silicon from the SOI wafer;
• forming a silicon layer on the SOI wafer;
• implanting a source drain junction beneath the segment of insulation;
• annealing the wafer;
• forming silicide on the silicon layer;
• removing the segment of insulation to create a gate cavity;
• and
• forming an insulated gate within the gate cavity, followed by conventional processing to complete the MOSFET device wherein the insulated gate is formed with a gate electrode which is insulated from the wafer by a high-k dielectric.