Self-aligned dual-oxide umosfet device and a method of fabricating same
AssigneeKoninklijke Philips Electronics N.V.
InventorTod Letavic
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Abstract
A self-aligned dual-oxide UMOSFET device and a method for fabricating the same which includes a gate in the trench which self-aligns the channel body doping region and its associated body-drift region junction, the region for depositing the gate insulating layer, and the depth of ledge for the field layer step for a sidewall of a trench using a multiple-energy large angle tilt implant (LATid) technique. One of the energy levels of the LATid technique is optimized to damage a top silicon nitride layer of the LOCOS mask. The other energy levels of the LATid technique are for the formation of the channel body region in substrate mesas adjacent the trench. Implantation occurs using the same tilt angle for the implantation of the channel dopant at the multiple-energy levels.
Claims11
A method of forming a self-aligned dual-oxide UMOSFET, comprising the steps of:
- etching a trench having sidewalls and a floor into a substrate;
- creating a gate in the trench by self-aligning a channel body doping region having a respective body-drift region junction, a region for depositing a gate insulating layer, and a depth of a field insulating layer step on a sidewall of the trench through implantation of a channel dopant at multiple-energy levels;
- and
- forming a source and a drain;
- further comprising the step of depositing in the trench and over the substrate a mask that includes an insulating layer having a first thickness, wherein the self-aligning step includes the steps of:
- implanting the channel doping at a first energy level through the mask in a substrate mesa adjacent to the sidewall of the trench to create the channel body doping region with a body-drift region junction therein;
- and
- implanting the channel doping at a second energy level to damage a portion of the mask along the body-drift region junction, wherein the damaged portion of the mask defines the region for depositing the gate insulating layer and the depth of the field insulating layer step.
Dependencies are inferred from the claim text.