Chip scale and land grid array semiconductor packages

A method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, the method comprising:

• providing a conductive leadframe;
• applying photo resist layer to a surface of the conductive leadframe and patterning the photo resist layer to expose a plurality of stud regions of the leadframe;
• plating the exposed stud regions on the conductive leadframe with nickel to form a nickel layer over the stud regions;
• plating the stud regions on the conductive leadframe with gold to form a gold layer over the nickel layers in the stud regions;
• stripping the photo resist from the surface of the conductive leadframe;
• and
• forming a plurality of etch resistant caps that cover a portion of the conductive leadframe immediately surrounding the perimeter of each of the nickel and gold layers;
• and
• etching the conductive leadframe areas surrounding each of the etch resistant caps to form depressed regions and a plurality of studs, whereby the depressed regions define the plurality of studs, wherein at least some of the studs are formed with locking grooves that are configured to allow a molding material to securely adhere to the studs.

A method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, the method comprising:

• providing a conductive leadframe;
• applying a photo resist layer to a surface of the conductive leadframe and patterning the photo resist layer to expose regions of the conductive leadframe;
• etching the exposed regions of the conductive leadframe to form depressed regions that define an array of suds in the conductive leadframe, wherein each of the studs have at least one locking groove that is configured to allow a molding material to securely adhere to the studs;
• stripping the photo resist from the surface of the conductive leadframe;
• and
• treating the etched conductive leadframe and the studs with a CZ treatment wherein the CZ treatment gives the conductive leadframe and the studs a surface finish that more easily bonds to the molding material.

A method for packaging integrated circuits, comprising the steps of:

• patterning a conductive substrate formed from a conductive material to define a plurality of studs and a connecting sheet connecting the plurality of studs, at least some of the studs including at least one locking groove;
• physically mounting a die on the patterned conductive substrate;
• electrically connecting the die to at least one of the plurality of studs;
• molding a molding cap over the die and the patterned conductive substrate, wherein the molding cap bonds to the surfaces of the studs and to the locking grooves;
• and
• removing the connecting sheet.