Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration

A semiconductor memory device comprising:

• a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns;
• a plurality of word lines arranged corresponding to said rows and each connected to memory cells of a corresponding row;
• a plurality of pairs of bit lines provided corresponding to said columns and each connected to memory cells of a corresponding column,
• wherein
• each of the pair of bit lines includes first and second bit lines transmitting data signals complementary to each other in a normal access mode,
• each memory cell of each column in each of said plurality of memory blocks is connected to one of said first and second bit lines of a corresponding pair of bit lines, and
• the plurality of word lines includes a first word line connected to a memory cell connected to the first bit line and a second word line connected to a memory cell connected to the second bit line;
• a plurality of sense amplifier groups each including a plurality of sense amplifier circuits, arranged corresponding to said plurality of memory blocks, each arranged to be shared by memory blocks adjacent to each other in a column direction, each of the sense amplifier circuits arranged corresponding to a column of a corresponding memory block and activated to sense and amplify data in a memory cell on a corresponding column;
• a plurality of bit line isolation circuits arranged between each of the sense amplifier groups and each memory block and each activated to isolate a corresponding sense amplifier group from a corresponding memory block;
• a plurality of bit line precharge circuit groups each including a plurality of bit line precharge circuits arranged corresponding to the columns of corresponding memory blocks, arranged to be shared by the memory blocks adjacent to each other in the column direction, each of the bit line precharge circuit groups being activated to transmit a voltage to the columns of a corresponding memory block;
• and
• a test control circuit for activating each of the bit line precharge circuits, inactivating said plurality of bit line isolation circuits and driving simultaneously, into selected state, a first predetermined number of word lines among said plurality of word lines in said plurality of memory blocks in a first test mode operation, and for inactivating said plurality of bit line precharge circuits, inactivating said plurality of bit line isolation circuits, driving simultaneously, into selected state, a second predetermined number of word lines among said plurality of word lines in said plurality of memory blocks, and activating said plurality of sense amplifier groups in a second test mode operation following the first test mode operation,
• wherein said test control circuit includes
• means configured for driving the first word lines into the selected state in response to activation of a first test instruction signal in said first test mode operation,
• means configured for setting said voltage transmitted by a voltage transmission line on a voltage transmission line at a voltage of a first logic level when said first test instruction signal is activated, and
• means configured to be responsive to activation of a second test instruction signal for simultaneously selecting said plurality of word lines in said plurality of memory blocks and setting the voltage on said voltage transmission line at a voltage of a second logic level in said first test mode operation, said second test instruction signal being activated prior to activation of said first test instructions signal.