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US 6,551,399 B1Granted
Fully integrated process for MIM capacitors using atomic layer deposition
AssigneeGenus, Inc.
InventorsOfer Sneh, Thomas E. Seidel
Life of this patent
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Abstract
A method and apparatus for fabricating a metal-insulator-metal capacitor by performing atomic layer deposition (ALD). A fully integrated process flow prevents electrode-dielectric contamination during an essential ex situ bottom electrode patterning step.
Claims12
A method of fabricating a metal-insulator-metal capacitor comprising:
- depositing a bottom conductive layer by atomic layer deposition;
- depositing a sacrificial layer, which is not a photoresist, above the bottom conductive layer by atomic layer deposition without exposing the bottom conductive layer to an ambient environment;
- exposing the sacrificial layer to an oxidizing ambient to undergo a photolithographic and etching processes that form a defined stacked structure by pattern delineating the bottom conductive and sacrificial layers;
- removing the sacrificial layer to expose the underlying bottom conductive layer without exposing the bottom conductive layer to the ambient environment;
- depositing a dielectric layer over the exposed bottom conductive layer by atomic layer deposition without exposing the bottom conductive layer to the ambient environment;
- depositing a top conductive layer over the dielectric layer without exposing the underlying dielectric layer to the ambient environment;
- and
- forming the top conductive layer over the defined stacked structure.
5 more elements
A method of fabricating a metal-insulator-metal capacitor comprising:
- depositing a bottom metal layer by atomic layer deposition;
- depositing a sacrificial layer comprised of metal above the bottom metal layer by atomic layer deposition without exposing the bottom metal layer to an ambient environment;
- exposing the sacrificial layer to an oxidizing ambient to undergo a photolithographic and etching processes that form a defined stacked structure by pattern delineating the bottom metal and sacrificial layers;
- removing the sacrificial layer to expose the underlying bottom metal layer by selective etch without exposing the bottom metal layer to the ambient environment and without etching the underlying bottom metal layer;
- depositing a dielectric layer over the exposed bottom metal layer by atomic layer deposition without exposing the bottom metal layer to the ambient environment;
- depositing a top metal layer over the dielectric layer without exposing the underlying dielectric layer to the ambient environment;
- and
- forming the top metal layer over the defined stacked structure.
5 more elements
Dependencies are inferred from the claim text.