Testing dies on a semiconductor wafer in a sequential and overlapping manner
OwnerEungjoon Parkinventor
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Abstract
In accordance with the present invention, a plurality of dies on a wafer are tested as follows. The wafer is placed in a tester. A built-in self test (BIST) operation is initiated in a first die. Another BIST operation is initiated in a second die after initiating the BIST operation in the first die such that the BIST operation in the first die and the BIST operation in the second die overlap.
Claims8
A method for testing a plurality of dies of a wafer, the method comprising:
- placing the wafer in a tester for testing the plurality of dies;
- initiating a built-in self test (BIST) operation in a first die;
- and
- initiating a BIST operation in a second die after initiating the BIST operation in the first die so that the BIST operation in the first die and the BIST operation in the second die overlap.
A method for testing a plurality of dies of a wafer wherein each of the plurality of dies has a circuit, a first contact pad configured to receive a power supply voltage, a second contact pad configured to receive a reference voltage, and a contact pad configured to receive a control signal for initiating a built-in self test (BIST) operation, the first and second pads being coupled to the circuit for powering the circuit, the method comprising:
- bringing at least three probe pins of a probe card into electrical contact with a respective one of the first, second, and third pads of a first die of the plurality of dies;
- initiating a BIST operation in the first die;
- removing the probe card from the first die;
- bringing the at least three probe pins of the probe card into electrical contact with a respective one of the first, second and third pads of a second die of the plurality of dies;
- and
- initiating a BIST operation in the second die,
- wherein the BIST operation in the first and second dies overlap.
Dependencies are inferred from the claim text.