Method of designing semiconductor integrated circuit device, and apparatus for designing the same

An apparatus for designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

• longest wiring load calculating unit for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;
• wiring load estimating unit for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell;
• and
• determining unit for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load and judging a signal inputted to the next-stage circuit cell to be drivable when the second load is smaller than the first load.

A recording medium having programs recorded therein for implementing the method of designing the semiconductor integrated circuit device, the medium controlling a computer by performing:

• a longest wiring load calculating operation calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;
• a wiring load estimating operation calculating, an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell;
• and
• a determining operation comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load in size, and judging a signal waveform inputted to the next-stage circuit cell to be less than or equal to a predetermined waveform rounding limit value and drivable when the second load is smaller than the first load.

A method of designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

• a longest wiring load calculating operation for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;
• a wiring load estimating operation for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell;
• and
• a determining operation for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load, and judging a delay for changing of the signal inputted to the next-stage circuit cell to be within an allowable time when the second load is smaller than the first load.

A method of designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

• a longest wiring load calculating operation for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;
• a wiring load estimating operation for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell;
• and
• a determining operation for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load,
• wherein a waveform of the signal inputted to the next-stage circuit cell has a waveform to be able to drive the next-stage circuit cell when the second load is smaller than the first load.

An apparatus for designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

• longest wiring load calculating unit for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;
• wiring load estimating unit for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load form the circuit cell of the next-stage circuit cell;
• and
• determining unit for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load, and judging a delay time for changing of the signal inputted to the next-stage circuit cell to be within an allowable time when the second load is smaller than the first load.

An apparatus for designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

• longest wiring load calculating unit for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;
• wiring load estimating unit for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit
• cell;
• and
• determining unit for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load, wherein a waveform of the signal inputted to the next-stage circuit cell has a waveform to be able to drive the next-stage circuit when the second load is smaller than the first load.