Semiconductor chip input/output cell design and automated generation methods

An automated method for generating input/output (I/O) cells for an integrated circuit chip, comprising:

• receiving a width parameter for a desired I/O cell to be used for the integrated circuit chip;
• receiving a tolerance parameter for the desired I/O cell;
• selecting a cell library having a plurality of slices, the cell library being selected to meet the tolerance parameter;
• determining a number of the plurality of slices to be used to fit within the width parameter and to satisfy a drive strength parameter;
• and
• filling the I/O cell within the width parameter with a first row of the determined number of the plurality of slices, wherein the plurality of slices of the cell library include N-type transistor slices, P-type transistor slices, cap slices, and receiver pre-driver slices.

A computer implemented method for automatically generating a custom I/O cell for an I/O region of a semiconductor chip, the I/O ring being defined around a core region of the semiconductor chip, the computer implemented method comprising:

• providing a selection form requesting user input of a desired I/O cell width and performance characteristics;
• receiving user input;
• selecting a cell slice width for cell slices to be obtained from a cell slice library;
• determining a transistor width requirement to meet the performance requirements;
• determining a height for the custom I/O cell, the height being selected so as to meet the transistor width requirement while maintaining the desired I/O cell width;
• and
• filling the desired I/O cell width with one or more of the cell slices having the determined height, the custom I/O cell being configured to at least meet the performance requirements.

A computer implemented method for automatically generating a custom I/O cell for an I/O region of a semiconductor chip, the I/O ring being defined around a core region of the semiconductor chip, the computer implemented method comprising:

• providing a selection form requesting user input of a desired I/O cell width and performance characteristics;
• receiving user input;
• selecting a cell slice width for cell slices to be obtained from a cell slice library;
• determining a transistor width requirement to meet the performance requirements;
• determining a height for the custom I/O cell, the height being selected so as to meet the transistor width requirement while maintaining the desired I/O cell width;
• filling the desired I/O cell width with one or more of the cell slices having the determined height, the custom I/O cell being configured to at least meet the performance requirements;
• and wherein the cell slice library includes cell slices for at least N-type transistor slices, P-type transistor slices, ring slices, and cap slices, and receiver slices.

A computer implemented method for automatically generating a custom I/O cell for an I/O region of a semiconductor chip, the I/O ring being defined around a core region of the semiconductor chip, the computer implemented method comprising:

• providing a selection form requesting user input of a desired I/O cell width and performance characteristics;
• receiving user input;
• selecting a cell slice width for cell slices to be obtained from a cell slice library;
• determining a transistor width requirement to meet the performance requirements;
• determining a height for the custom I/O cell, the height being selected so as to meet the transistor width requirement while maintaining the desired I/O cell width;
• filling the desired I/O cell width with one or more of the cell slices having the determined height, the custom I/O cell being configured to at least meet the performance requirements;
• and
• distributing a plurality of the custom I/O cells around the I/O region, the distributing of the custom I/O cells including the layout of associated bond pads to interface with each of the plurality of the custom I/O cells.

A method for generating an I/O cell and an associated bond pad, the I/O cell and the bond pad designed to be replicated around a core region of an integrated circuit chip, the method comprising:

• receiving a pad pitch parameter;
• receiving user defined performance characteristics, the performance characteristics including,
• a drive strength parameter;
• receiving a selection of one of an in-line pad arrangement and a staggered pad arrangement;
• and
• generating an I/O cell having an I/O cell width and a configured height, the configured height being defined to meet the performance characteristics.

A method for generating an I/O cell and an associated bond pad, the I/O cell and the bond pad designed to be replicated around a core region of an integrated circuit chip, the method comprising:

• receiving a pad pitch parameter;
• receiving user defined performance characteristics, the performance characteristics including,
• a drive strength parameter;
• receiving a selection of one of an in-line pad arrangement and a staggered pad arrangement;
• generating an I/O cell having an I/O cell width and a configured height, the configured height being defined to meet the performance characteristics;
• and
• wherein the performance characteristics further include,
• a tolerance parameter;
• an input level parameter;
• an input buffer style parameter;
• a slew rate parameter;
• a ring voltage parameter;
• and
• a bond pad top layer metal parameter.

A computer readable media containing program instructions for generating input/output (I/O) cells for an integrated circuit chip, the computer readable media comprising:

• program instructions for receiving a width parameter for a desired I/O cell to be used for the integrated circuit chip;
• program instructions for receiving a tolerance parameter for the desired I/O cell;
• program instructions for selecting a cell library having a plurality of slices, the selection being configured to select cells meeting the tolerance parameter;
• program instructions for determining a number of the plurality of slices to be used to fit within the width parameter and to satisfy a drive strength parameter;
• and
• program instructions for filling the I/O cell within the width parameter with a first row of the determined number of the plurality of slices.

A computer implemented method for automatically generating a custom I/O cell for an I/O region of a semiconductor chip, the I/O ring being defined around a core region of the semiconductor chip, the computer implemented method comprising:

• selecting a cell slice width for cell slices to be obtained from a cell slice library;
• determining a transistor width requirement to meet a tolerance parameter;
• determining a height for the custom I/O cell, the height being selected so as to meet the tolerance parameter while maintaining the desired I/O cell width;
• and
• filling the desired I/O cell width with one or more of the cell slices having the determined height, the custom I/O cell being configured to at least meet the tolerance parameter.