US 6,550,045 B1 · Changing clock delays in an integrated circuit for skew optimization

Abstract

Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.

Claims16

Dependent claims

A process of designing a clock network of an ASIC to change clock delays, the clock network having a plurality of clock sources each having a clock domain, and the ASIC further includes data circuits that define timing paths between at least two clock domains, the process comprising steps of:

a) selecting clock cells to be changed in the clock network;
b) calculating a slack for each selected clock cell based on an insertion delay associated with at least one clock source and clock arrival and transition times required by the selected clock cell;
c) adjusting cell delay based on the calculated slack
d) identifying at least one group of clock domains having timing paths between member domains;
e) equalizing clock insertion delays for all clock domains of the group;
and
f) altering clock insertion delays for clock domains in each group to minimize slack.

4 more elements

A storage medium having stored therein processor executable instructions that enable a processor to change clock delays in a clock network design for an ASIC having a plurality of clock sources, and the ASIC further includes data circuits that define timing paths between at least two clock domains, the processor executable instructions include:

selection instructions that enable the processor to select clock cells to be changed in the clock network design;
calculating instructions that enable the processor to calculate a slack for each selected clock cell based on an insertion delay associated with at least one clock source and clock arrival and transition times required by the selected clock cell;
adjusting instructions that enable the processor to adjust cell delay based on the calculated slack;
identifying instructions that enable the processor to identify at least one group of clock domains having timing paths between member domains;
insertion instructions that enable the processor to equalize clock insertion delays for all clock domains of the group;
and
altering instructions that enable the processor to alter clock insertion delays for clock domains in each group to minimize slack.

4 more elements

Dependencies are inferred from the claim text.

Changing clock delays in an integrated circuit for skew optimization

Life of this patent

Changing clock delays in an integrated circuit for skew optimization

Life of this patent

Abstract

Claims16