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US 6,550,044 B1Granted
Method in integrating clock tree synthesis and timing optimization for an integrated circuit design
AssigneeLSI Logic Corporation
InventorsIvan Pavisic, Aiguo Lu, Andrej A. Zolotykh, Elyar E. Gasanov
Life of this patent
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Abstract
A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.
Claims9
A method of synthesizing a clock tree for an integrated circuit design comprising the steps of:
- (a) constructing an initial balanced clock tree for an integrated circuit design;
- (b) calculating a clock arrival time for each clock driven cell in the initial clock tree;
- (c) performing a timing analysis from the clock arrival time calculated for each corresponding clock driven cell;
- (d) if a signal path having a first hold time violation is detected by the timing analysis, then inserting a first buffer to delay the clock arrival time at the corresponding clock driven cell by a first selected delay time to correct the first hold time violation;
- and
- (e) if a second hold time violation is introduced in a second signal path by the insertion of the first buffer, then inserting a second buffer in the second signal path to delay a signal arrival time by a second selected delay time to correct the second hold time violation.
3 more elements
A computer program product comprising:
- a medium for embodying a computer program for input to a computer;
- and
- a computer program embodied in the medium for causing the computer to perform the following functions:
- (a) constructing an initial balanced clock tree for an integrated circuit design;
- (b) calculating a clock arrival time for each clock driven cell in the initial clock tree;
- (c) performing a timing analysis from the clock arrival time calculated for each corresponding clock driven cell;
- (d) it a signal path having a first hold time violation is detected by the timing analysis, then inserting a first butter to delay the clock arrival time at the corresponding clock driven cell by a first selected delay time to correct the first hold time violation;
- and
- (e) if a second hold time violation is introduced in a second signal path by the insertion of the first buffer, then inserting a second buffer in the second signal path to delay a signal arrival time by a second selected delay time to correct the second hold time violation wherein step (d) comprises inserting the first buffer delay at a clock input of the corresponding clock driven cell in the balanced clock tree.
6 more elements
A computer program product comprising:
- a medium for embodying a computer program for input to a computer;
- and
- a computer program embodied in the medium for causing the computer to perform the following functions:
- (a) constructing an initial balanced clock tree for an integrated circuit design;
- (b) calculating a clock arrival time for each clock driven cell in the initial clock tree;
- (c) performing a timing analysis from the clock arrival time calculated for cacti corresponding clock driven cell;
- (d) if a signal path having a first hold time violation is detected by the timing analysis, then inserting a first buffer to delay the clock arrival time at the corresponding clock driven cell by a first selected delay time to correct the first hold time violation;
- and
- (e) if a second hold time violation is introduced in a second signal path by the insertion of the first buffer, then inserting a second buffer in the second signal path to delay a signal arrival time by a second selected delay time to correct the second hold time violation wherein the first buffer is selected so as not to create a hold timing violation in another signal path.
6 more elements
A computer program product comprising:
- a medium for embodying a computer program for input to a computer;
- and
- a computer program embodied in the medium for causing the computer to perform the following functions:
- (a) constructing an initial balanced clock tree for an integrated circuit design;
- (b) calculating a clock arrival time for each clock driven cell in the initial clock tree;
- (c) performing a timing analysis from the clock arrival time calculated for each corresponding clock driven cell;
- (d) if a signal path having a first hold time violation is detected by the timing analysis, then inserting a first buffer to delay the clock arrival time at the corresponding clock driven cell by a first selected delay time to correct the first hold time violation;
- and
- (e) if a second hold time violation is introduced in a second signal path by the insertion of the first buffer, then inserting a second buffer in the second signal path to delay a signal arrival time by a second selected delay time to correct the second hold time violation wherein step (e) comprises inserting the second buffer in a signal path between two clock driven cells.
6 more elements
A computer program product comprising:
- a medium for embodying a computer program for input to a computer;
- and
- a computer program embodied in the medium for causing the computer to perform the following functions:
- (a) constructing an initial balanced clock tree for an integrated circuit design;
- (b) calculating a clock arrival time for each clock driven cell in the initial clock tree;
- (c) performing a timing analysis from the clock arrival time calculated for each corresponding clock driven cell;
- (d) if a signal path having a first hold time violation is detected by the timing analysis, then inserting a first buffer to delay the clock arrival time at the corresponding clock driven cell by a first selected delay time to correct the first hold time violation;
- and
- (e) if a second hold time violation is introduced in a second signal path by the insertion of the first buffer, then inserting a second buffer in the second signal path to delay a signal arrival time by a second selected delay time to correct the second hold time violation further comprising updating the balanced clock tree when a buffer is inserted therein for concurrent analysis of timing problems during cell placement.
6 more elements
Dependencies are inferred from the claim text.