Semiconductor device with clock signal selection circuit

A semiconductor device comprising:

• a CPU,
• an address decoder that decodes an address signal transmitted from the CPU and outputs an address area specifying signal for specifying an address area in which a designated address is included,
• a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered,
• a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from said address decoder,
• a disable register, into which data can be written by the CPU, and
• a logic circuit connected to said disable register, wherein when a predetermined value is written into said disable register, the function of said clock signal decision circuit is disabled, and a base clock signal can be always input to the CPU.

A semiconductor device comprising:

• a CPU,
• an address decoder that decodes an address signal transmitted from the CPU and outputs an address area specifying signal for specifying an address area in which a designated address is included,
• a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered,
• a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from said address decoder, and
• a clock specifying register composed of a plurality of clock specifying bits, into which data can be written by the CPU, and each corresponding to the respective one of a predetermined number of divided address areas, wherein each of said clock specifying bits instructs to said clock signal decision circuit as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU.

A semiconductor device comprising:

• a CPU,
• an address decoder that decodes an address signal transmitted from the CPU and outputs an address area specifying signal for specifying an address area in which a designated address is included,
• a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered,
• a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from said address decoder, and
• a frequency specifying register composed of a plurality of frequency specifying bits, into which data can be written by the CPU, each corresponding to the respective one of a plurality of stages in a multi-stage frequency divider, wherein each of said frequency specifying bits instructs to said clock signal decision circuit as to which one of the clock signals is to be input to the CPU, the division rates of said clock signals being different from one another obtainable from each of said multi-stage frequency divider composed of a plurality of flip-flops.

A semiconductor device comprising:

• a CPU,
• an address decoder that decodes an address signal transmitted from the CPU and outputs an address area specifying signal for specifying an address area in which a designated address is included,
• a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered,
• a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from said address decoder,
• a clock specifying register composed of a plurality of clock specifying bits, into which data can be written by the CPU, and each corresponding to the respective one of a predetermined number of divided address areas, wherein each of said clock specifying bits instructs to said clock signal decision circuit as to which one of the base clock signal and the frequency-divided clock signal is to be input to the CPU, and
• a frequency specifying register composed of a plurality of frequency specifying bits, into which data can be written by the CPU, each corresponding to the respective one of a plurality of stages in a multi-stage frequency divider, wherein each of said frequency specifying bits instructs to said clock signal decision circuit as to one which of the clock signals is to be input to the CPU, the division rates of said clock signals being different from one another obtainable from each of said multi-stage frequency divider composed of a plurality of flip-flops.