US 6,550,042 B1 · Hardware/software co-synthesis of heterogeneous low-power and fault-tolerant systems-on-a chip

Abstract

The present co-synthesis technique takes as an input embedded system specification in terms of acyclic task graphs, system constraints, and a resource library consisting of several functional blocks such as processor cores, memory, proprietary and non-proprietary functional blocks, and generates a low-cost hardware and software architecture for systems-on-a-chip such that all real time constraints are met while minimizing average power dissipation. It employs a floor-planning based delay estimator during evaluation of various architectures. Actual delay measurements made on synthesized chips indicate that the delay estimator error is less than 12%. The technique can be extended to derive fault-tolerant architectures for systems-on-a-chip employed in critical applications. Fault-detection capability is imparted to the system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. Error recovery is achieved by switching to spare functional blocks. The reliability and availability of the architecture are evaluated during co-synthesis using Markov models. Application of the technique to examples from real-life systems such a cellular hand sets, video set-top boxes, frame relay interfaces, and Asynchronous Transfer Mode (ATM) switch controllers shows its efficacy. The technique is able to achieve up to 90% cost reduction by employing a systems-on-a-chip concept when compared to architectures employing discrete devices. The technique optimizes both power and fault-tolerance overhead.

Claims14

Dependent claims

A computer-implemented method for designing an architecture of an embedded system-on-a-chip (SOC), comprising:

(a) a pre-processing phase comprising the step of parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded SOC;
and
(b) a synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the task graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the task graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, to generate a current version of the embedded SOC, wherein, prior to the performance evaluation for a current allocation, floor-planning is performed to update a delay estimate for each of one or more of the allocated edges in the current version of the embedded SOC, wherein, during the floor-planning, PEs are placed into a floor plan in order of decreasing connectivity index, wherein the connectivity index for a PE represents a number of communication links to and from the PE.

Dependencies are inferred from the claim text.

Hardware/software co-synthesis of heterogeneous low-power and fault-tolerant systems-on-a chip

Life of this patent

Hardware/software co-synthesis of heterogeneous low-power and fault-tolerant systems-on-a chip

Life of this patent

Abstract

Claims14