Method and apparatus for evaluating the design quality of network nodes

A rules checker computer program embodied on a computer-readable medium, the program calculating an effective wire resistance at a receiver node of a receiver gate comprised in an integrated circuit, the effective wire resistance being associated with a network of the integrated circuit, the network comprising a driver connected by a conductive path to the receiver node, the conductive path having a parasitic resistance associated therewith, the program comprising:

• code for traversing the conductive path from an output node of the driver gate to the receiver node of the receiver gate, the code summing parasitic resistances encountered along the path and maintaining a total of the summed parasitic resistances, wherein when the code determines that all of the parasitic resistances between the output node of the driver and the receiver node of the receiver have been summed, the code determines that the total is equal to the effective wire resistance at the receiver node.

A method for determining an effective wire resistance of a network comprised in an integrated circuit, the method comprising the steps of:

• executing a rules checker program in a computer, wherein when the rules checker program is executed by the computer, the rules checker program analyzes information relating to the network to determine an effective wire resistance at a receiver node of a receiver gate of the network, the effective wire resistance being associated with one or more individual parasitic resistances along a conductive path of the network that connects a driver gate of the network to the receiver node, the effective wire resistance corresponding to a total of the values of all of the parasitic resistances along the path summed together.

An apparatus for determining an effective wire resistance of a network comprised in an integrated circuit, the apparatus comprising:

• means for analyzing information relating to the network to determine an effective wire resistance at a receiver node of a receiver gate of the network, the effective wire resistance being associated with one or more individual parasitic resistances inherent in a conductive path of the network that connects a driver gate of the network to said receiver node, said means calculating the effective wire resistance by summing the values of the parasitic resistances along the path from the driver gate to the receiver node.