Method and system for identifying dynamic NAND or NOR gates from a netlist
AssigneeHewlett-Packard Development Company, L.P.
InventorsS. Brandon Keller, Gregory Dennis Rogers
Life of this patent
Estimating the term…
Abstract
A method for identifying dynamic NAND or NOR gates from a netlist having output nodes, supply voltages along with their opposite supply voltages, FETs and their connections, which includes the steps of selecting an output node from the netlist, identifying FETs having at least one branch that is connected directly to the selected output node but not connected directly to the supply voltage, verifying that the branch(es) of the identified FETs define a dynamic logic gate, and identifying either a NAND gate or a NOR gate for the dynamic logic gate.
Claims11
A method for identifying dynamic NAND or NOR gates from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, said method comprising the steps of:
- selecting an output node from the netlist;
- identifying FETs having at least one branch that are connected directly to the selected output node but not connected directly to the supply voltage;
- verifying that said at least one branch of the identified FETs define a dynamic logic gate;
- and,
- identifying either a NAND gate or a NOR gate for the dynamic logic gate.
A computer system for identifying dynamic NAND or NOR gates from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, comprising:
- a storage medium;
- a processor for executing a program stored on the storage medium for identifying dynamic NAND or NOR gates from a netlist, the program comprising a set of instructions for:
- selecting an output node from the netlist;
- identifying FETs having at least one branch that are connected directly to the selected output node but not connected directly to the supply voltage;
- verifying that said at least one branch of the identified FETs define a dynamic logic gate;
- and,
- identifying either a NAND gate or a NOR gate for the dynamic logic gate.
A computer program product comprising a computer usable medium having computer readable program codes embodied in the medium that when executed causes a computer to:
- selecting an output node from the netlist;
- identifying FETs having at least one branch that are connected directly to the selected output node but not connected directly to the supply voltage;
- verifying that said at least one branch of the identified FETs define a dynamic logic gate;
- and,
- identifying either a NAND gate or a NOR gate for the dynamic logic gate.
Dependencies are inferred from the claim text.